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    Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
    7.
    发明授权
    Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
    避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法

    公开(公告)号：US07091128B2

    公开(公告)日：2006-08-15

    申请号：US11266855

    申请日：2005-11-04

    申请人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A. Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A. Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

    摘要翻译： 描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。 在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。 在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。 使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。 然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”） 遗迹。 插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。 通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。 因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

    Metal oxynitride as a pFET material
    10.
    发明授权
    Metal oxynitride as a pFET material 失效
    金属氮氧化物作为pFET材料

    公开(公告)号：US07776701B2

    公开(公告)日：2010-08-17

    申请号：US12190129

    申请日：2008-08-12

    申请人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

    发明人： Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Sufi Zafar

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/469 ,  H01L21/31 ,  H01L21/8234

    CPC分类号： H01L21/28088 ,  H01L21/823828 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

    摘要翻译： 包含MoxNy的复合金属是具有在包括高k电介质和界面层的栅叠层上热稳定的功函数为约4.75至约5.3，优选约5e的功函数的p型金属，以及 制造MOxNy复合金属的方法。 此外，本发明的MOxNy金属化合物在1000℃下是非常有效的氧扩散阻挡层，允许在p金属氧化物半导体（pMOS）器件中非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度 。 在上式中，M是选自元素周期表第IVB，VB，VIB或VIIB族的金属，x为约5至约40原子％，y为约5至约40原子％。