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21.发明授权Dedicated input/output first in/first out module for a field programmable gate array 失效用于现场可编程门阵列的专用输入/输出先进先出模块公开(公告)号：US07102385B2
公开(公告)日：2006-09-05
申请号：US11295889
申请日：2005-12-06
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.
摘要翻译： 具有多个输入/输出焊盘的现场可编程门阵列架构包括：多个逻辑簇; 多个输入/输出群集; 多个输入/输出缓冲器; 多个专用输入/输出先进先出存储块，专用输入/输出先进先出存储块具有耦合到多个输入/输出存储器中的一个的先进先出存储器， 输出垫; 以及可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连架构，其中专用输入/输出先入先出存储器块可编程地耦合在输入/输出缓冲器和输入/ 输出集群。
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公开(公告)号：US06980028B1
公开(公告)日：2005-12-27
申请号：US11056983
申请日：2005-02-11
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory. The dedicated input/output first-in/first-out memory comprising a plurality of input/output clusters coupled to the input/output pads of the field programmable gate array and a plurality of input/output block controllers coupled to said input/output clusters.
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公开(公告)号：US06976185B1
公开(公告)日：2005-12-13
申请号：US10722636
申请日：2003-11-25
CPC分类号： G06F1/10
摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。
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24.发明授权Dedicated input/output first in/first out module for a field programmable gate array 有权用于现场可编程门阵列的专用输入/输出先进先出模块公开(公告)号：US06867615B1
公开(公告)日：2005-03-15
申请号：US10452764
申请日：2003-05-30
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory. The dedicated input/output first-in/first-out memory comprising a plurality of input/output clusters coupled to the input/output pads of the field programmable gate array and a plurality of input/output block controllers coupled to said input/output clusters.
摘要翻译： 具有多个输入/输出焊盘和专用输入/输出先进先出存储器的现场可编程门阵列。 专用输入/输出先进先出存储器包括耦合到现场可编程门阵列的输入/输出焊盘的多个输入/输出群集和耦合到所述输入/输出群集的多个输入/输出块控制器 。
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公开(公告)号：US06718477B1
公开(公告)日：2004-04-06
申请号：US09519311
申请日：2000-03-06
IPC分类号： G06F108
CPC分类号： G06F1/10
摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。
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公开(公告)号：US07941685B2
公开(公告)日：2011-05-10
申请号：US12337201
申请日：2008-12-17
IPC分类号： G06F1/08
CPC分类号： G06F1/10
摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。
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公开(公告)号：US20090094475A1
公开(公告)日：2009-04-09
申请号：US12337201
申请日：2008-12-17
IPC分类号： G06F1/08
CPC分类号： G06F1/10
摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。
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28.发明申请REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS 有权在具有划分的轨迹的现场可编程门阵列中生成非均匀路由架构的可重复块公开(公告)号：US20080246510A1
公开(公告)日：2008-10-09
申请号：US12131258
申请日：2008-06-02
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译： 在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹 在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。
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29.发明授权Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks 有权可重复块在具有分段轨道的现场可编程门阵列中产生非均匀路由架构公开(公告)号：US07385420B1
公开(公告)日：2008-06-10
申请号：US11426541
申请日：2006-06-26
申请人： Arunangshu Kundu , Eric Sather , William C. Plants
发明人： Arunangshu Kundu , Eric Sather , William C. Plants
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , G11C5/063 , H01L27/118
摘要： A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
摘要翻译： 在现场可编程门阵列中的可重复的非均匀分段路由架构，包括：可重复的路由轨道块，所述路由轨迹被分组为路由轨道集合，每个路由集合具有处于第一轨道位置的第一路由轨道，第二路由轨迹 在最后轨道位置，可编程元件和用于对可编程元件进行编程的直接地址设备; 其中所述路由轨道中的至少一个由所述可编程元件分段成非均匀长度，并且所述第二路由轨道在与所述可重复块的边缘相邻的区域中跨越到所述第一轨道位置; 并且其中第一多个所述路线轨迹组在水平方向上行进，并且所述第二多个所述路线轨迹组在垂直方向上进行。
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30.发明授权Dedicated input/output first in/first out module for a field programmable gate array 失效用于现场可编程门阵列的专用输入/输出先进先出模块公开(公告)号：US07199609B1
公开(公告)日：2007-04-03
申请号：US11428944
申请日：2006-07-06
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A method of forming a field programmable gate array architecture having a plurality of input/output pads comprising: providing a plurality of logic clusters; providing a plurality of input/output clusters; providing a plurality of input/output buffers; providing a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; providing an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks, wherein the input/output block controller comprises a dedicated FIFO flag logic block and an input/output FIFO block controller cluster; and providing a routing interconnect architecture programmably coupling the logic clusters, the input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.
摘要翻译： 一种形成具有多个输入/输出焊盘的现场可编程门阵列结构的方法，包括：提供多个逻辑簇; 提供多个输入/输出群集; 提供多个输入/输出缓冲器; 提供多个专用输入/输出先进先出存储块，所述专用输入/输出先进先出存储块具有耦合到所述多个输入中的一个输入的先进先出存储器 /输出板; 提供可编程地耦合到所述多个专用输入/输出先进先出存储块的输入/输出块控制器，其中所述输入/输出块控制器包括专用FIFO标志逻辑块和输入/输出FIFO块控制器簇 ; 以及提供可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连结构，其中专用输入/输出先入先出存储块可编程地耦合在输入/输出缓冲器和 输入/输出集群。
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