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21.
公开(公告)号:US12101979B2
公开(公告)日:2024-09-24
申请号:US17435363
申请日:2021-03-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jiangnan Lu , Libin Liu , Jie Zhang , Mei Li , Yuhan Qian , Shiming Shi
IPC: H10K59/12 , H10K50/813 , H10K50/824 , H10K59/131 , H10K71/00 , H10K59/35
CPC classification number: H10K59/1315 , H10K50/813 , H10K50/824 , H10K71/00 , H10K59/1201 , H10K59/351
Abstract: The display substrate includes: a substrate, an auxiliary cathode layer, a first insulating layer, an anode layer, a second insulating layer, and a cathode layer that are sequentially stacked on the substrate in a direction away from the substrate; the anode layer includes a plurality of anode patterns spaced apart from each other, and an anode spacing area is formed between adjacent anode patterns; an orthographic projection of the auxiliary cathode layer on the substrate and an orthographic projection of the cathode layer on the substrate have an auxiliary overlapping area, and the auxiliary cathode layer is electrically connected to the cathode layer through a connection via hole in the auxiliary overlapping area; an orthographic projection of the connection via hole on the substrate is located inside the orthographic projection of the anode spacing area on the substrate.
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公开(公告)号:US20240215344A1
公开(公告)日:2024-06-27
申请号:US17788605
申请日:2021-08-30
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yu Feng , Libin Liu , Jiangnan Lu
IPC: H10K59/131 , G09G3/32
CPC classification number: H10K59/131 , G09G3/32 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233 , G09G2320/0247
Abstract: An array substrate is provided. A respective pixel driving circuit of the array substrate includes a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor. An active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer. The active layer of the driving transistor comprises a first semiconductor material. The active layer of the transistor comprises a second semiconductor material different from the first semiconductor material.
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公开(公告)号:US11963407B2
公开(公告)日:2024-04-16
申请号:US17427076
申请日:2020-11-13
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiangnan Lu , Guangliang Shang , Can Zheng , Yu Feng , Libin Liu , Jie Zhang , Mei Li
IPC: H10K59/131 , G09G3/3208 , H10K59/121
CPC classification number: H10K59/131 , H10K59/121 , G09G3/3208 , G09G2320/0209 , G09G2320/0233
Abstract: Provided is an organic light-emitting diode display substrate, including: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein the source/drain layer includes at least one pair of first signal lines; the anode layer includes a common power line, wherein the common power line is provided with vent holes; overlapping areas between two first signal lines in each pair of the first signal lines and a projection pattern of the vent hole are equal, the overlapping area being greater than 0, wherein the projection pattern of the vent hole is a pattern of an orthographic projection of the vent hole in the common power line on the source/drain layer. A display panel and a display device are also provided.
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24.
公开(公告)号:US11915655B2
公开(公告)日:2024-02-27
申请号:US17631780
申请日:2021-03-05
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiangnan Lu , Guangliang Shang , Xinshe Yin , Libin Liu , Ke Feng
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2300/0408 , G09G2310/0286
Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.
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公开(公告)号:US20230320160A1
公开(公告)日:2023-10-05
申请号:US18022367
申请日:2022-03-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Lujiang Huangfu , Weiwei Wang , Shanshan Bai , Jiangnan Lu , Wenxiu Zhu
IPC: H10K59/35 , G02F1/1343
CPC classification number: H10K59/353 , H10K59/352 , G02F1/134345
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a plurality of sub-pixels in rows. The sub-pixels in each row includes first sub-pixels, second sub-pixels and third sub-pixels arranged alternately, and two adjacent rows of sub-pixels are arranged in a staggered manner. In every two adjacent rows of sub-pixels, each first sub-pixel in one row of sub-pixels and the second sub-pixel and the third sub-pixel adjacent to the first sub-pixel in another row of sub-pixels form a pixel. White brightness centers of the pixels in a same pixel row are located on a same straight line, and a brightness center of the first sub-pixel is not on a same straight line as the brightness centers of the second sub-pixel and the third sub-pixel located in a same sub-pixel row.
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26.
公开(公告)号:US11763740B2
公开(公告)日:2023-09-19
申请号:US17762330
申请日:2021-04-15
Applicant: BOE Technology Group Co., Ltd.
Inventor: Guangliang Shang , Libin Liu , Tian Dong , Jiangnan Lu , Shiming Shi
IPC: G09G3/20 , G09G3/3208 , G11C19/28 , G09G3/3225
CPC classification number: G09G3/3225 , G11C19/28 , G09G2300/0426 , G09G2300/0852 , G09G2310/0286 , G09G2310/08 , G09G2320/0223 , G09G2320/0233 , G09G2320/0247
Abstract: The present disclosure provides a signal generation circuit, a signal generation method, a signal generation module and a display device. The signal generating circuit includes an input terminal, a signal output terminal, a transmission control circuit, a first output circuit, and an output control circuit; the output control circuit is electrically connected to a first output control terminal, a second output control terminal, a second voltage terminal, the signal writing-in terminal, the signal output terminal and the first voltage terminal, configured to control to connect the signal writing-in terminal and the second voltage terminal under the control of a second output control signal provided by the second output control terminal, and control to connect the signal output terminal and the first voltage terminal under the control of a first output control signal provided by the first output control terminal. The present disclosure expands an adjustment range of frequency of a PWM signal.
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27.
公开(公告)号:US20230162685A1
公开(公告)日:2023-05-25
申请号:US17631780
申请日:2021-03-05
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiangnan Lu , Guangliang Shang , Xinshe Yin , Libin Liu , Ke Feng
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2310/0286 , G09G2300/0408
Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: an input control circuit, configured to control a level of the first node; a first control circuit, configured to control a level of the second node; a second control circuit, configured to control the level of the second node under control of a fourth clock signal and an output signal; an output circuit, configured to control a level of the output terminal under control of the level of the first node and the level of the second node; and a first reset circuit, configured to control the level of the output terminal under control of the first enable signal, so as to allow the output terminal to stably output a non-operating level during a detection phase.
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28.
公开(公告)号:US11387305B2
公开(公告)日:2022-07-12
申请号:US16475471
申请日:2018-08-10
Applicant: BOE Technology Group Co., Ltd.
Inventor: Shi Shu , Jiangnan Lu , Xing Zhang , Wei Liu , Zhengliang Li , Cuili Gai
IPC: H01L27/32 , H01L51/56 , H01L29/786
Abstract: The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a plurality of thin film transistors on the base substrate; and a plurality of semiconductor junctions configured to shield light from irradiating on active layers of the plurality of thin film transistors.
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公开(公告)号:US11385494B2
公开(公告)日:2022-07-12
申请号:US16649550
申请日:2019-09-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yang Yue , Shi Shu , Chuanxiang Xu , Haitao Huang , Xiang Li , Jiangnan Lu , Qi Yao
IPC: G02F1/1335 , G02F1/13357 , G02F1/1333
Abstract: A color filter substrate, a manufacturing method thereof and a display device are provided. The color filter substrate includes: a base substrate; a black matrix on the base substrate, the black matrix including a plurality of openings and a bank surrounding each opening; a color filter layer in each opening; a first planarization layer covering the color filter layer, and the bank protruding relative to the first planarization layer in a direction away from the base substrate; a second planarization layer covering both the first planarization layer and the bank, the second planarization layer including a first surface distal to the base substrate; and a grating layer on the second planarization layer. The first surface of the second planarization layer includes a first portion and a second portion, an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of the plurality of openings on the base substrate, an orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of the bank on the base substrate, and a vertical distance between the first portion and a surface of the base substrate close to the second planarization layer is greater than a vertical distance between the second portion and the surface of the base substrate close to the second planarization layer.
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公开(公告)号:US20210223655A1
公开(公告)日:2021-07-22
申请号:US16303358
申请日:2017-12-07
Applicant: BOE Technology Group Co., Ltd.
Inventor: Shi Shu , Chuanxiang Xu , Jiangnan Lu , Yang Yue , Yue Shi
IPC: G02F1/157 , H01L27/32 , G02F1/155 , G09G3/38 , G09G3/3225
Abstract: The present application discloses a display panel having an array of a plurality of subpixels. The display panel includes a plurality of light modulators configured to modulate display contrast of the display panel. Each of the plurality of light modulators is in a light modulation region configured to allow light transmitting through the display panel. Light transmittance in the light modulation region is controlled by a first gate line and a first data line for driving image display in a first subpixel of the plurality of subpixels.
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