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公开(公告)号：US20220311652A1
公开(公告)日：2022-09-29
申请号：US17418272
申请日：2020-12-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yang ZHANG
IPC: H04L41/046 , H04L41/069
Abstract: The present disclosure relates to an intelligent network management system. The intelligent network management system includes: a plurality of terminals, including at least one management terminal and at least one application terminal; and at least one server, coupled to the management terminal and the application terminal, and including a data management circuit, a service management circuit, and an application management circuit, the management terminal being configured to send a data management signal, a service management signal and an application management signal to the server, the data management circuit performing data layer management on the application terminal in response to the data management signal, the service management circuit performing service layer management on the application terminal in response to the service management signal, and the application management circuit performing application layer management on the application terminal in response to the application management signal.
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公开(公告)号：US20210313356A1
公开(公告)日：2021-10-07
申请号：US16761231
申请日：2019-10-28
Inventor： Ning LIU , Bin ZHOU , Jun LIU , Yang ZHANG , Tongshang SU , Haitao WANG
Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.
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23.发明申请公开(公告)号：US20210227656A1
公开(公告)日：2021-07-22
申请号：US16756467
申请日：2019-10-21
Inventor： Qinghe WANG , Dongfang WANG , Tongshang SU , Ning LIU , Guangyao LI , Yongchao HUANG , Yang ZHANG , Jiawen SONG , Zhiwen LUO , Liangchen YAN
IPC: H05B45/18 , H01L29/786 , H01L31/12 , H01L29/49 , H01L29/423 , H01L27/32
Abstract: A thin-film transistor includes: an active layer having a first side and a second side opposing to the first side; a main gate electrode spaced from the active layer on the first side, and including a conductive material; an auxiliary gate electrode spaced from the active layer on the second side, wherein the auxiliary gate electrode includes a phase change material having a phase change temperature; the auxiliary gate electrode is configured to have a transition between insulating and conductive based on a temperature of the auxiliary gate electrode; and the main gate electrode and the auxiliary gate electrode are electrically coupled to each other when the auxiliary gate electrode is conductive.
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公开(公告)号：US20210183329A1
公开(公告)日：2021-06-17
申请号：US16087280
申请日：2018-01-04
Inventor： Jian ZHAO , Huanyu LI , Mo CHEN , Jilei GAO , Yang ZHANG
Abstract: A common voltage compensation circuit unit including a trigger signal terminal, a common voltage output terminal, a design common voltage signal terminal, a power signal terminal, a compensation common voltage signal terminal, a reset signal terminal, a clock signal terminal, a trigger signal input sub-circuit, a first output sub-circuit, a control sub-circuit, a second output sub-circuit, and a reset sub-circuit. The present disclosure further provides a display panel, a display device, and a common voltage compensation method for a display panel.
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公开(公告)号：US20210074946A1
公开(公告)日：2021-03-11
申请号：US17051323
申请日：2020-03-02
Inventor： Leilei CHENG , Tongshang SU , Qinghe WANG , Guangyao LI , Wei SONG , Ning LIU , Yang ZHANG , Yongchao HUANG
Abstract: The present invention relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a first electrode layer. The first electrode layer may include an indium tin oxide layer and a planarization layer. The indium tin oxide layer is disposed on a substrate and includes indium tin oxide particles; the planarization layer is disposed on a side of the indium tin oxide layer away from the substrate, and fills at least part of gaps between the indium tin oxide particles, and the planarization layer can conduct electricity.
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Patent Agency Ranking
公开(公告)号：US20200168687A1
公开(公告)日：2020-05-28
申请号：US16441422
申请日：2019-06-14
Inventor： Yingbin HU , Liangchen YAN , Ce ZHAO , Yuankui DING , Yang ZHANG , Yongchao HUANG , Luke DING , Jun LIU
Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.
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公开(公告)号：US20200075704A1
公开(公告)日：2020-03-05
申请号：US16456619
申请日：2019-06-28
Inventor： Jun LIU , Liangchen YAN , Bin ZHOU , Jun WANG , Tongshang SU , Biao LUO , Yang ZHANG
Abstract: An array substrate includes a base substrate, a transistor on the base substrate, a planarization layer on a side of the transistor away from the base substrate, a recessed portion on the planarization layer, and a light blocking portion in the recessed portion. The light blocking portion is configured to prevent a light from being incident upon an active layer.
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28.发明申请公开(公告)号：US20200064734A1
公开(公告)日：2020-02-27
申请号：US16458341
申请日：2019-07-01
Inventor： Wei LI , Jingjing XIA , Bin ZHOU , Jun LIU , Tongshang SU , Yang ZHANG , Liangchen YAN
Abstract: Disclosed are a photoresist composition, a pixel definition structure and a manufacturing method thereof, and a display panel. The photoresist composition includes an organic film-forming resin, a superhydrophobic polymerizable monomer, a polyfunctional crosslinkable polymerizable monomer, a photoinitiator, an additive and a solvent.
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公开(公告)号：US20190100838A1
公开(公告)日：2019-04-04
申请号：US16119012
申请日：2018-08-31
Inventor： Jifeng SHAO , Guangcai YUAN , Tongshang SU , Yang ZHANG , Qinghe WANG , Yingbin HU
IPC: C23C16/40 , H01L51/52 , H01L51/00 , C23C16/455
Abstract: The present disclosure relates to a copper nanofiber, its preparation method and a display panel. The copper nanofiber comprises a copper nanofiber body, an aluminum-doped zinc oxide layer disposed at the external surface of the copper nanofiber body, and a passivation layer disposed on a side of the aluminum-doped zinc oxide layer away from the copper nanofiber body.
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30.发明申请公开(公告)号：US20190080779A1
公开(公告)日：2019-03-14
申请号：US15768487
申请日：2017-09-26
Inventor： Yang ZHANG , Jinliang LIU , Mo CHEN , Jian ZHAO , Jilei GAO , Songmei SUN
Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.
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