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1.发明申请公开(公告)号：US20190173028A1
公开(公告)日：2019-06-06
申请号：US15991134
申请日：2018-05-29
发明人： Jun WANG , Guangyao LI , Dongfang WANG , Jun LIU , Guangcai YUAN , Leilei CHENG
摘要： The present disclosure relates to a substrate, a method for fabricating the same and an organic light emitting diode display device. The substrate includes a metal foil. A metal material used for the metal foil is capable of being anodized and a plurality of concave light trapping microstructures is formed on a surface of the metal foil.
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公开(公告)号：US20200171426A1
公开(公告)日：2020-06-04
申请号：US16611417
申请日：2019-01-22
发明人： Guangyao LI , Guangcai YUAN , Dongfang WANG , Jun WANG , Qinghe WANG , Wei LI , Leilei CHENG
摘要： The present disclosure provides a gas screening film including at least one gas screening element, each of the at least one gas screening element includes a transistor including a gate, an insulation spacing layer, a first electrode, a semiconductor nanosheet separation layer and a second electrode, and the insulation spacing layer is disposed between the gate and the semiconductor nanosheet separation layer. The present disclosure further provides a manufacturing method of the gas screening film and a face mask. The gas screening film can screen and separate various different gases as necessary.
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3.发明申请公开(公告)号：US20190172953A1
公开(公告)日：2019-06-06
申请号：US15992909
申请日：2018-05-30
发明人： Yuankui DING , Ce ZHAO , Guangcai YUAN , Yingbin HU , Leilei CHENG , Jun CHENG , Bin ZHOU
IPC分类号： H01L29/786 , H01L27/12 , H01L29/66
摘要： The present disclosure discloses a TFT, a manufacturing method, an array substrate, a display panel, and a device. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.
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公开(公告)号：US20190100838A1
公开(公告)日：2019-04-04
申请号：US16119012
申请日：2018-08-31
发明人： Jifeng SHAO , Guangcai YUAN , Tongshang SU , Yang ZHANG , Qinghe WANG , Yingbin HU
IPC分类号： C23C16/40 , H01L51/52 , H01L51/00 , C23C16/455
摘要： The present disclosure relates to a copper nanofiber, its preparation method and a display panel. The copper nanofiber comprises a copper nanofiber body, an aluminum-doped zinc oxide layer disposed at the external surface of the copper nanofiber body, and a passivation layer disposed on a side of the aluminum-doped zinc oxide layer away from the copper nanofiber body.
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5.发明申请公开(公告)号：US20190067608A1
公开(公告)日：2019-02-28
申请号：US15949112
申请日：2018-04-10
发明人： Qinghe WANG , Jinliang HU , Rui PENG , Dongfang WANG , Guangcai YUAN
IPC分类号： H01L51/05 , H01L51/10 , H01L51/00 , H04R31/00 , H04R7/06 , H04R1/40 , H04R3/00 , H04R19/00 , H04R19/04 , G01H11/06
摘要： The present disclosure provides a transistor acoustic sensor element and a method for manufacturing the same, an acoustic sensor and a portable device. The transistor acoustic sensor element comprises a gate, a gate insulating layer, a first electrode, an active layer and a second electrode arranged on a base substrate, wherein the active layer has a nanowire three-dimensional mesh structure and thus can vibrate under the action of sound signals, so that the output current of the transistor acoustic sensor element changes correspondingly. Since the active layer having the nanowire three-dimensional mesh structure can sensitively sense weak vibration of acoustic waves, the sensitivity to sound signals of the transistor acoustic sensor element is improved.
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公开(公告)号：US20200033290A1
公开(公告)日：2020-01-30
申请号：US16453637
申请日：2019-06-26
发明人： Qinghe WANG , Liangchen YAN , Dongfang WANG , Tongshang SU , Leilei CHENG , Yongchao HUANG , Yang ZHANG , Guangyao LI , Guangcai YUAN
IPC分类号： G01N27/414 , H01L27/32 , H01L51/00
摘要： Embodiments of the present disclosure relate to the field of electronic sensing technologies, and provide a chemical sensing unit, a chemical sensor, and a chemical sensing device. The chemical sensing unit includes a thin film transistor arranged on a substrate, and a light emitting diode coupled to the thin film transistor. The thin film transistor includes a semiconductor active layer, a source, and a drain, and the semiconductor active layer is mainly composed of a chemically sensitive semiconductor material. The chemical sensing unit is provided with a via hole in a region between the source and the drain, such that the semiconductor active layer is exposed at a position corresponding to the via hole. The light emitting diode includes a first electrode, a light-emitting functional layer, and a second electrode which are stacked in sequence, wherein the first electrode is coupled to the drain.
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7.发明申请公开(公告)号：US20190386144A1
公开(公告)日：2019-12-19
申请号：US16554657
申请日：2019-08-29
发明人： Yuankui DING , Ce ZHAO , Guangcai YUAN , Yingbin HU , Leilei CHENG , Jun CHENG , Bin ZHOU
IPC分类号： H01L29/786 , H01L27/12 , H01L29/66
摘要： A thin film transistor (TFT), a manufacturing method, an array substrate, a display panel, and a device is disclosed. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.
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公开(公告)号：US20240329478A1
公开(公告)日：2024-10-03
申请号：US18638710
申请日：2024-04-18
发明人： Guangcai YUAN , Hehe HU , Ce NING , Hui GUO , Fengjuan LIU , Dongfang WANG , Zhengliang LI , Jiayu HE
IPC分类号： G02F1/1368 , G02F1/1362 , H01L27/12
CPC分类号： G02F1/1368 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136295 , H01L27/124 , H01L27/1255 , H01L27/1259
摘要： An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.
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公开(公告)号：US20240324335A1
公开(公告)日：2024-09-26
申请号：US18245553
申请日：2022-01-30
发明人： Jinxiang XUE , Zhongyuan SUN , Wenqi LIU , Jingkai NI , Che AN , Guangcai YUAN , Lu WANG , Fang LIU , Xiaohu LI , Liangliang KANG , Zhiqiang JIAO , Peng WANG
IPC分类号： H10K59/131 , H10K59/121 , H10K59/122 , H10K59/18 , H10K59/80 , H10K77/10 , H10K102/00
CPC分类号： H10K59/131 , H10K59/1213 , H10K59/1216 , H10K59/122 , H10K59/18 , H10K59/873 , H10K77/111 , H10K2102/311
摘要： The present disclosure provides a display panel and a display device. The display panel includes: a substrate; a plurality of display units arranged on a side of the substrate, each of the plurality of display units including at least one sub-pixel; a plurality of elastic stretching units arranged on a side of the substrate, each of the plurality of elastic stretching units being connected between two adjacent display units, and a plurality of hollow regions being formed between the plurality of elastic stretching units and the plurality of display units. A sum of areas of the plurality of hollow regions is a, a sum of areas of the plurality of display units is b, and a sum of areas of the plurality of elastic stretching units is c; 15%≤a/(a+b+c)×100%≤30%.
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公开(公告)号：US20240178238A1
公开(公告)日：2024-05-30
申请号：US17789505
申请日：2021-06-24
发明人： Dongfang WANG , Ce NING , Guangcai YUAN
IPC分类号： H01L27/12
CPC分类号： H01L27/1244 , H01L27/1222 , H01L27/1251 , H01L27/127
摘要： An array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. The first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. The first wiring pattern is connected with the first interconnection pattern through a via hole. Each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. The first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.
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