Network processor for multiprotocol data flows
    26.
    发明授权
    Network processor for multiprotocol data flows 有权
    用于多协议数据流的网络处理器

    公开(公告)号:US06671280B1

    公开(公告)日:2003-12-30

    申请号:US09535794

    申请日:2000-03-29

    IPC分类号: H04L1256

    摘要: A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.

    摘要翻译: 公开了一种在电信网络内集成异步传输模式(ATM)和基于帧的业务流的方法。 电信网络包括具有上行处理装置的网络处理器,用于将来自电信网络的输入流传送到交换机,以及下行处理装置,用于将来自交换机的输出网络业务传送到电信网络。 最初在上行处理装置处接收输入流作为基于帧的流。 输入流可以被表征为属于具有基于帧的流和ATM流的组。 响应于接收到的流入,确定进入流是否发往传统的仅ATM设备。 然后根据确定的路由要求和输入流特性,将传入流量传送到交换机之前处理进入流。

    Queue manager for a buffer
    27.
    发明授权
    Queue manager for a buffer 失效
    队列管理器为缓冲区

    公开(公告)号:US06557053B1

    公开(公告)日:2003-04-29

    申请号:US09477179

    申请日:2000-01-04

    IPC分类号: G06F1314

    CPC分类号: G06F13/1673

    摘要: A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

    摘要翻译: 提供了用于FIFO缓冲器的带宽保存队列管理器,优选地在ASIC芯片上,并且优选地包括分离的DRAM存储器,其维持FIFO队列,其可以超出FIFO缓冲器的数据存储空间,以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间,则不需要额外的数据存储。 然而,当超过FIFO缓冲器中的一些预定量的缓冲存储空间时,数据被写入附加数据存储器并从其中读出,并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包,以及哪个 被写入数据存储设备,使得它们以先入先出(FIFO)地址序列排队。 优选地,以突发模式将数据写入DRAM并从DRAM读取。