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102 条记录 (耗时 0.034 秒)

    Network processor/software control architecture
    5.
    发明授权
    Network processor/software control architecture 失效
    网络处理器/软件控制架构

    公开(公告)号：US06898179B1

    公开(公告)日：2005-05-24

    申请号：US09544896

    申请日：2000-04-07

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Colin Beaton Verrilli ,  Fabrice Jean Verplanken

    IPC分类号： G06F11/00 ,  H04B7/216 ,  H04L1/16 ,  H04L12/26

    CPC分类号： G06F15/17

    摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.

    摘要翻译： 提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。 在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。 典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。 提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。 为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

    Network processor probing and port mirroring
    8.
    发明授权
    Network processor probing and port mirroring 失效
    网络处理器探测和端口镜像

    公开(公告)号：US06449576B1

    公开(公告)日：2002-09-10

    申请号：US09538247

    申请日：2000-03-29

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Chad Everett Winemiller

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Chad Everett Winemiller

    IPC分类号： G01R2728

    CPC分类号： H04L43/50 ,  G01R31/31926

    摘要： A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.

    摘要翻译： 一种用于系统地访问和监视IC设备内的操作参数信号的方法和系统。 探针配置逻辑从IC器件的物理或逻辑细分内的一组可用信号中选择一个信号子集。 信号访问逻辑选择性地从IC器件的物理或逻辑细分中的选定的信号子集提供到探针传感器的物理或逻辑访问，使得可以灵活和全面地监视IC器件操作。 本地模式选择器可在输入/输出（I / O）数据接口上远程访问选定的信号子集。 与探头传感器通信的数据封装逻辑允许端口镜像I / O数据接口。

    Full match (FM) search algorithm implementation for a network processor
    9.
    发明授权
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US07139753B2

    公开(公告)日：2006-11-21

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F7/00 ,  H04L12/28

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Method and apparatus for processing frame classification information between network processors
    10.
    发明授权
    Method and apparatus for processing frame classification information between network processors 失效
    用于处理网络处理器之间帧分类信息的方法和装置

    公开(公告)号：US07106730B1

    公开(公告)日：2006-09-12

    申请号：US09546833

    申请日：2000-04-11

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/30

    摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

    摘要翻译： 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。