公开(公告)号：US20060049845A1

公开(公告)日：2006-03-09

申请号：US10937000

申请日：2004-09-08

申请人： James Jaussi ,  Bryan Casper

发明人： James Jaussi ,  Bryan Casper

IPC分类号： H03K19/173

CPC分类号： H04L25/03057 ,  H04L2025/03356 ,  H04L2025/0349

摘要： In one embodiment, a decision feedback equalizer helps mitigate intersymbol interference in a bi-directional signaling environment. In the particular embodiment, the decision feedback equalizer includes a voltage-to-current converter to source a received differential current to first and second node, a latch to provide logic signal when comparing currents sourced to the first and second nodes, a memory unit to store the logic signals, and a mapping circuit to source first and second feedback currents to the first and second nodes. This embodiment further includes a transmitter to transmit data over a transmission line during receiving, and a digital-to-analog converter to provide a differential current to the first and second nodes to substantially cancel that part of the received differential currents contributed by the transmitter. In this embodiment, the mapping circuit may comprise a lookup table to map the stored logic signals into code words, and another digital-to-analog converter to source differential current to the first and second nodes in response to the code words. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，判决反馈均衡器有助于减轻双向信令环境中的符号间干扰。 在特定实施例中，判决反馈均衡器包括电压 - 电流转换器，用于将接收的差分电流输出到第一和第二节点;锁存器，当比较源自第一和第二节点的电流时提供逻辑信号;存储器单元， 存储逻辑信号，以及映射电路，以将第一和第二反馈电流输出到第一和第二节点。 该实施例还包括在接收期间通过传输线传输数据的发射机和数模转换器，以向第一和第二节点提供差分电流，以基本上消除由发射机贡献的所接收差分电流的那部分。 在该实施例中，映射电路可以包括查找表，以将所存储的逻辑信号映射成码字，以及另一个数模转换器，以响应于码字来向第一和第二节点输出差分电流。 描述和要求保护其他实施例。

公开(公告)号：US20060036668A1

公开(公告)日：2006-02-16

申请号：US11181380

申请日：2005-07-14

申请人： James Jaussi ,  Bryan Casper ,  Aaron Martin

发明人： James Jaussi ,  Bryan Casper ,  Aaron Martin

IPC分类号： G06G7/02

CPC分类号： G06G7/16 ,  H03H11/1213

摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。

公开(公告)号：US20070233444A1

公开(公告)日：2007-10-04

申请号：US11395537

申请日：2006-03-31

申请人： Frank O'Mahony ,  Haydar Kutuk ,  Bryan Casper ,  Eyal Fayneh ,  Sivakumar Mudanai ,  Wei-kai Shih ,  Farag Fattouh

发明人： Frank O'Mahony ,  Haydar Kutuk ,  Bryan Casper ,  Eyal Fayneh ,  Sivakumar Mudanai ,  Wei-kai Shih ,  Farag Fattouh

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

摘要翻译： 通常，在一个方面，本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。 模拟器能够为晶体管以及无源元件（如电阻）增加噪声。 模拟器使用与设备并联的至少一个电流源来模拟噪声。 电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。 可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。 模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱（例如，热噪声，闪烁噪声）的任何噪声源。 模拟器与标准电路模拟器兼容。

公开(公告)号：US20070147491A1

公开(公告)日：2007-06-28

申请号：US11317162

申请日：2005-12-22

申请人： Bryan Casper ,  James Jaussi

发明人： Bryan Casper ,  James Jaussi

IPC分类号： H03K5/159

CPC分类号： H04L25/03885 ,  H04L25/0272

摘要： According to embodiments of the subject matter disclosed in this application, transmit equalization, systematic jitter correction, and jitter injection may be achieved through a lookup table transmitter equalizer. The equalizer may be a multiple-way interleaving equalizer, with each interleaved section having its own lookup table. Entries in each lookup table may be modified to correct systematic jitters occurring in the received signal. Additionally, random errors may be injected to each lookup table. Injected errors are converted to both amplitude and phase modulation across a channel. By measuring the signal at the receiver, the characteristics of the transmission line may be obtained.

摘要翻译： 根据本申请中公开的主题的实施例，可以通过查找表发射机均衡器来实现发射均衡，系统抖动校正和抖动注入。 均衡器可以是多路交织均衡器，其中每个交织部分具有其自己的查找表。 可以修改每个查找表中的条目以校正在接收信号中发生的系统抖动。 另外，随机错误可以被注入每个查找表。 注入的误差被转换为跨通道的幅度和相位调制。 通过测量接收机的信号，可以获得传输线的特性。

公开(公告)号：US20050151566A1

公开(公告)日：2005-07-14

申请号：US10995950

申请日：2004-11-23

申请人： James Jaussi ,  Bryan Casper

发明人： James Jaussi ,  Bryan Casper

IPC分类号： H03K3/356 ,  H03K5/24 ,  H03K5/22

CPC分类号： H03K3/356191 ,  H03K3/35613 ,  H03K5/249

摘要： A comparator unit comprising a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential amplifier having a pair of input nodes for receiving a differential signal and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes. The second amplifier stage is coupled to the pair of output nodes of the first amplifier stage. In one embodiment the second amplifier stage is a non-linear amplifier. In an alternative embodiment, the differential amplifier is a differential pair. In another alternative embodiment, the differential amplifier is a pair of differential pairs.

摘要翻译： 比较器单元，包括第一放大器级和第二放大级。 第一放大器级包括差分放大器，其具有用于接收差分信号的一对输入节点和一对输出节点，跨越该对输出节点连接的开关和跨该对输出节点连接的非线性负载。 第二放大器级耦合到第一放大器级的一对输出节点。 在一个实施例中，第二放大器级是非线性放大器。 在替代实施例中，差分放大器是差分对。 在另一替代实施例中，差分放大器是一对差分对。

公开(公告)号：US20050286644A1

公开(公告)日：2005-12-29

申请号：US10880308

申请日：2004-06-28

申请人： James Jaussi ,  Bryan Casper

发明人： James Jaussi ,  Bryan Casper

IPC分类号： H03H21/00 ,  H04B3/00

CPC分类号： H03H21/0001

摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.

摘要翻译： 在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是 第二个二进制值。 每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。 使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。 在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。 在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。 本发明的实施例具有对信道均衡的应用。

公开(公告)号：US20100164539A1

公开(公告)日：2010-07-01

申请号：US12347858

申请日：2008-12-31

申请人： Ganesh Balamurugan ,  Bryan Casper

发明人： Ganesh Balamurugan ,  Bryan Casper

IPC分类号： H03K17/16

CPC分类号： H03K19/018585

摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

摘要翻译： 对于广泛的I / O系统要求可重新配置的收发器。 可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。 可以对所有发送模式预先强调要传输的信号。 可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

公开(公告)号：US07919984B2

公开(公告)日：2011-04-05

申请号：US12347858

申请日：2008-12-31

申请人： Ganesh Balamurugan ,  Bryan Casper

发明人： Ganesh Balamurugan ,  Bryan Casper

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585

摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

摘要翻译： 对于广泛的I / O系统要求可重新配置的收发器。 可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。 可以对所有发送模式预先强调要传输的信号。 可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

公开(公告)号：US20060139199A1

公开(公告)日：2006-06-29

申请号：US11027477

申请日：2004-12-28

申请人： Bryan Casper ,  Craig Petrie

发明人： Bryan Casper ,  Craig Petrie

IPC分类号： H03M1/12

CPC分类号： H03M1/403

摘要： A cyclic analog to digital converter (ADC) circuit operates to convert an analog input voltage into a digital output word. The ADC circuit includes an amplifier and capacitors configured as an integrator.

摘要翻译： 循环模数转换器（ADC）电路用于将模拟输入电压转换为数字输出字。 ADC电路包括配置为积分器的放大器和电容器。

公开(公告)号：US20060139195A1

公开(公告)日：2006-06-29

申请号：US11025579

申请日：2004-12-29

申请人： Bryan Casper ,  Craig Petrie

发明人： Bryan Casper ,  Craig Petrie

IPC分类号： H03M1/66

CPC分类号： H03M1/667

摘要： A digital to analog converter (DAC) circuit operates least significant bit (LSB) first.

摘要翻译： 数模转换器（DAC）电路首先运行最低有效位（LSB）。