公开(公告)号：US10073934B1

公开(公告)日：2018-09-11

申请号：US15290362

申请日：2016-10-11

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Arun Kumar Mishra

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/10

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

公开(公告)号：US09928324B1

公开(公告)日：2018-03-27

申请号：US14264695

申请日：2014-04-29

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  William Franson Scott

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F2217/84

Abstract: A system, method, and computer program product for modeling a receiver load in static timing analysis of digital circuits. Embodiments separate total receiver charge into static and dynamic components, and extract both from an improved library model. The receiver load is effectively modeled with a static capacitance and a current source connected in parallel. A method of extracting load model characteristics from a standard timing library is also provided. The improved receiver model reflects the physical phenomena not currently modeled, and enables a more accurate description of circuit behavior while still using a simple approximation of the transistor level circuit. The complete circuit switching response is found through a perturbative approach, combining a linear response using constant capacitance values with a correction having time-dependent charges for modeling physical phenomena such as the back-Miller effect. The result is improved circuit timing evaluation, with good accuracy versus SPICE simulation for waveforms and delays.

公开(公告)号：US09582626B1

公开(公告)日：2017-02-28

申请号：US14549424

申请日：2014-11-20

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Eddy Pramono ,  Jijun Chen ,  Nikolay Rubanov

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/84

Abstract: Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.

Abstract translation: 除了传统的摆动信息之外，还使用详细的波形信息来执行STA期间的精确时序分析。 波形存储器系统有效地存储在电路设计的定时分析中使用，计算和传播的详细波形。 在STA过程中，对于电路设计的多个建模阶段，包括波形形式的信息的波形被压缩，存储，解压缩并从存储器系统检索。 存储系统提供存储效率，包括长期和短期存储区域，多级存储以及在STA期间评估的每个视图的单独存储。

公开(公告)号：US08938703B1

公开(公告)日：2015-01-20

申请号：US14338272

申请日：2014-07-22

Applicant: Cadence Design Systems, Inc.

Inventor： Sneh Saurabh ,  Naresh Kumar ,  Igor Keller

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs that are necessary for the identification and removal of common path pessimism, the timing information of the topologically crucial points of the design block will be retained in the ETM, and the non-essential and noisy information will be removed from the ETM to ensure that the ETM is robust and compact.

Abstract translation: 用于生成提取时序模型（ETM）的系统和方法用于分析集成电路设计的时序，其中有助于通用路径悲观（CPP）的共同路径被识别并包含在生成的ETM中，使得CPP去除 在时序分析过程中实现的算法将被适当调整，以消除这种悲观情绪。 为了生成ETM，时钟延迟路径将被特征化，考虑到识别和消除公共路径悲观情况所需的引脚和定时弧，设计块的拓扑关键点的定时信息将保留在 ETM和非必要和嘈杂的信息将从ETM中删除，以确保ETM稳健且紧凑。

公开(公告)号：US08726211B2

公开(公告)日：2014-05-13

申请号：US13632885

申请日：2012-10-01

Applicant: Cadence Design Systems, Inc.

Inventor： Joel R. Phillips ,  Qunzeng Liu ,  Igor Keller

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/84

Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

Abstract translation: 提供了一种用于在集成电路设计的静态时序分析期间用于产生等效波形模型的方法，所述方法包括：使用内部组件的模拟模型来模拟内部组件以产生多个模拟仿真输出表征波形作为 用于表征设计单元的多个输入波形的功能; 使用内部组件的模拟模型来模拟内部组件，以产生作为复杂波形的函数的模拟仿真输出波形; 并产生等效波形模型作为多个模拟仿真输出特性波形和模拟仿真输出波形的函数。