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    High performance static timing analysis system and method for input/output interfaces
    3.
    发明授权
    High performance static timing analysis system and method for input/output interfaces 有权
    高性能静态时序分析系统及输入/输出接口方法

    公开(公告)号：US09405882B1

    公开(公告)日：2016-08-02

    申请号：US14752206

    申请日：2015-06-26

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Amit Dhuria ,  Naresh Kumar ,  Prashant Sethia ,  Jeannette Sutherland ,  Shashank Tripathi

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

    Abstract: A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

    Abstract translation: 一种用于集成电路设计的输入/输出模式的静态时序分析方法，其包括以硬件描述语言描述的集成电路设计加载到存储器中。 定义了静态时序分析的活动区域，其包括输入/​​输出端口与输入端口上游和输出端口下游的顺序逻辑元件的选定级别之间的逻辑和互连。 使用硬件描述语言生成活动区域的描述。 然后对活动区域的逻辑执行静态时序分析。

    System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design
    4.
    发明授权
    System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design 有权
    指导由物理实施数据定义的电路设计的补救变换的系统和方法，以减少电路设计中检测到的定时违规所需的物理校正

    公开(公告)号：US08788995B1

    公开(公告)日：2014-07-22

    申请号：US13842178

    申请日：2013-03-15

    Applicant: Cadence Design Systems, Inc.

    Inventor： Naresh Kumar ,  Prashant Sethia ,  Amit Dhuria ,  Krishna Belkhale

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

    Abstract translation: 提供了一种系统和方法，用于减少为电路设计的优化提供的定时数据库的悲观情绪。 通过生成基于混合图的静态时序分析（GBA）和基于路径的静态时序分析（PBA STA）数据库来减少悲观。 选择性地对最关键的GBA识别的定时违规执行PBA，目的是减少传递到物理实现校正优化器模块的操作时序特性的错误悲观，从而减少电路设计上的不必要的固定和转换，从而相应地减少设计时间 存储空间，所需的处理能力用于定时关闭，并且导致完成的可操作和有形的电路装置，其面积减小，功率要求低，成本降低。

    System and method for generating and using a structurally aware timing model for representative operation of a circuit design
    8.
    发明授权
    System and method for generating and using a structurally aware timing model for representative operation of a circuit design 有权
    用于生成和使用结构感知定时模型以用于电路设计的代表性操作的系统和方法

    公开(公告)号：US08863052B1

    公开(公告)日：2014-10-14

    申请号：US13940576

    申请日：2013-07-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Amit Dhuria ,  Naresh Kumar ,  Umesh Gupta ,  Pradeep Yadav ,  Prashant Sethia

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

    Abstract translation: 提供了一种用于产生用于预定电路设计的操作的结构感知定时模型的系统和方法。 产生定时模型以具有表示电路设计的定时特性的多个定时弧。 另外，评估电路设计的端子对以确定通过电路设计的所选路径的特征结构权重。 结构感知定时模型然后可以被并入到顶级分级电路设计中，用于定时分析和悲观消除以达到实际的定时特性。 结构重量在AOCV型悲观消除后期处理中特别有用。

    Infinite-depth path-based analysis of operational timing for circuit design
    10.
    发明授权
    Infinite-depth path-based analysis of operational timing for circuit design 有权

    公开(公告)号：US10776547B1

    公开(公告)日：2020-09-15

    申请号：US16600927

    申请日：2019-10-14

    Applicant: Cadence Design Systems, Inc.

    Inventor： Umesh Gupta ,  Naresh Kumar ,  Prashant Sethia ,  Ritika Govila ,  Jayant Sharma

    IPC: G06F30/3312 ,  G06F16/901 ,  G06F119/12

    Abstract: A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.

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