公开(公告)号：US20120156885A1

公开(公告)日：2012-06-21

申请号：US12974714

申请日：2010-12-21

申请人： Chang-Hsiao LEE ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

发明人： Chang-Hsiao LEE ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/465

CPC分类号： H01L21/02063 ,  H01L21/67207 ,  H01L21/76814

摘要： In a method for processing a semiconductor wafer formed with a copper conductor, the semiconductor wafer is etched in an etching chamber to expose the copper conductor. The etched semiconductor wafer is transmitted from the etching chamber to a buffer zone, where a gas inert to the semiconductor wafer is introduced for a period of time. Then the semiconductor wafer is moved out of the buffer zone to a loading module. Nitrogen is one of the suitable options as the gas, and argon is another option.

摘要翻译： 在用铜导体形成的半导体晶片的处理方法中，在蚀刻室中蚀刻半导体晶片以露出铜导体。 蚀刻的半导体晶片从蚀刻室传输到缓冲区，其中对半导体晶片惰性的气体被引入一段时间。 然后将半导体晶片从缓冲区移出到加载模块。 氮气是气体的合适选择之一，氩气是另一种选择。

公开(公告)号：US20110139750A1

公开(公告)日：2011-06-16

申请号：US12637762

申请日：2009-12-15

申请人： Chang-Hsiao Lee ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

发明人： Chang-Hsiao Lee ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC分类号： C23F1/00

CPC分类号： H01L21/31144 ,  H01L21/02071 ,  H01L21/32138

摘要： A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.

摘要翻译： 提供了去除蚀刻后残留物的方法。 首先，提供基板。 隔离层覆盖基板，并且导电层嵌入在隔离层中。 介电层和硬掩模覆盖隔离层。 然后，进行蚀刻处理，通过用离子或原子蚀刻硬掩模来形成图案化的硬掩模。 之后，通过使用导电溶液来清洁图案化的硬掩模和电介质层，从而去除在刻蚀过程中累积在图案化的硬掩模和电介质层上的电荷，进行电荷去除处理。 最后，去除图案化硬掩模和电介质层上的蚀刻后残留物。

公开(公告)号：US08735295B2

公开(公告)日：2014-05-27

申请号：US13526554

申请日：2012-06-19

申请人： Chang-Hsiao Lee ,  Hsin-Yu Chen ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao ,  Shih-Chun Tsai

发明人： Chang-Hsiao Lee ,  Hsin-Yu Chen ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao ,  Shih-Chun Tsai

IPC分类号： H01L21/311

CPC分类号： H01L21/302 ,  H01L21/76811 ,  H01L21/76813

摘要： A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.

摘要翻译： 一种用于制造双镶嵌结构的方法包括以下步骤。 首先，在基板上依次形成电介质层，电介质掩模层和金属掩模层。 在金属掩模层中形成多个沟槽开口，并且金属掩模层的一部分露出在每个沟槽开口的底部。 随后，在介电掩模层中形成多个通路孔，并且电介质掩模层的一部分暴露在每个通路孔的底部。 此外，沟槽开口和通孔开口被转移到电介质层以形成多个双镶嵌开口。

公开(公告)号：US20130337650A1

公开(公告)日：2013-12-19

申请号：US13526554

申请日：2012-06-19

申请人： Chang-Hsiao Lee ,  Hsin-Yu Chen ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao ,  Shih-Chun Tsai

发明人： Chang-Hsiao Lee ,  Hsin-Yu Chen ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao ,  Shih-Chun Tsai

IPC分类号： H01L21/302

CPC分类号： H01L21/302 ,  H01L21/76811 ,  H01L21/76813

摘要： A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.

摘要翻译： 一种用于制造双镶嵌结构的方法包括以下步骤。 首先，在基板上依次形成电介质层，电介质掩模层和金属掩模层。 在金属掩模层中形成多个沟槽开口，并且金属掩模层的一部分露出在每个沟槽开口的底部。 随后，在介电掩模层中形成多个通路孔，并且电介质掩模层的一部分暴露在每个通路孔的底部。 此外，沟槽开口和通孔开口被转移到电介质层以形成多个双镶嵌开口。

公开(公告)号：US08101092B2

公开(公告)日：2012-01-24

申请号：US11877918

申请日：2007-10-24

申请人： Chih-Wen Feng ,  Pei-Yu Chou ,  Chun-Ting Yeh ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Ying-Chih Lin

发明人： Chih-Wen Feng ,  Pei-Yu Chou ,  Chun-Ting Yeh ,  Jyh-Cherng Yau ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Ying-Chih Lin

IPC分类号： C03C15/00 ,  H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76816 ,  H01L21/76897

摘要： A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.

摘要翻译： 提供了一种用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 首先，使用图案化的光致抗蚀剂层作为掩模进行第一蚀刻步骤，以在其侧壁上形成图案化的含Si材料层和聚合物层。 接下来，利用图案化的光致抗蚀剂层，图案化的含Si材料层和聚合物层作为掩模来执行第二蚀刻步骤，以至少去除蚀刻电阻层的暴露部分以形成图案化的蚀刻电阻层。 通过使用图案化的蚀刻电阻层作为蚀刻掩模来去除目标材料层的一部分，以在靶材料层中形成第一和第二开口。 该方法的特征在于控制第一和第二蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US20080064176A1

公开(公告)日：2008-03-13

申请号：US11531260

申请日：2006-09-12

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

摘要翻译： 一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上 形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分 去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。 因此，当去除间隔物时，材料层可被保护层保护。

公开(公告)号：US20070238238A1

公开(公告)日：2007-10-11

申请号：US11389617

申请日：2006-03-24

申请人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

发明人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

IPC分类号： H01L21/8238 ,  H01L29/80

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

摘要翻译： 提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。 衬底具有由隔离结构隔开的第一有源区和第二有源区。 此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。 第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。 第一衬里层顺应地设置在第一应力层上。 第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

公开(公告)号：US20120264279A1

公开(公告)日：2012-10-18

申请号：US13085787

申请日：2011-04-13

申请人： Shui-Yen LU ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shih-Fang Tzou ,  Shin-Chin Chen

发明人： Shui-Yen LU ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shih-Fang Tzou ,  Shin-Chin Chen

IPC分类号： H01L21/28

CPC分类号： H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a semiconductor structure comprising a substrate, a dummy gate structure having a dielectric layer disposed over the substrate and a silicon layer disposed over the dielectric layer, and an etching stop layer (ESL) and an inter-layer dielectric (ILD) layer both of which are sequentially disposed over the substrate and the dummy gate structure is first provided. Then, a chemical mechanical polishing (CMP) is performed to planrizing the ILD layer and expose the ESL. Subsequently, an in-situ etching process is conducted to remove portions of the ESL and the silicon layer to form an opening in the dummy gate structure. Next, metal material is filled into the opening.

摘要翻译： 一种制造半导体器件的方法，其中所述方法包括以下步骤：包括衬底的半导体结构，设置在所述衬底上的电介质层的伪栅极结构和设置在所述电介质层上的硅层，以及蚀刻停止层 （ESL）和层间电介质（ILD）层，它们都顺序地设置在衬底上，并且首先提供虚拟栅极结构。 然后，进行化学机械抛光（CMP）以平整ILD层并暴露ESL。 随后，进行原位蚀刻工艺以去除ESL和硅层的部分以在虚拟栅极结构中形成开口。 接下来，将金属材料填充到开口中。

公开(公告)号：US20110076814A1

公开(公告)日：2011-03-31

申请号：US12959393

申请日：2010-12-03

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US20110068408A1

公开(公告)日：2011-03-24

申请号：US12959399

申请日：2010-12-03

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.

摘要翻译： 应变硅CMOS晶体管包括：具有第一有源区，第二有源区和设置在第一有源区和第二有源区之间的隔离结构的半导体衬底; 第一晶体管，设置在第一有源区上; 第二晶体管，设置在第二有源区上; 第一蚀刻停止层，设置在第一晶体管和第二晶体管上; 第一应力层，设置在所述第一晶体管上; 第二蚀刻停止层，设置在第一晶体管和第一应力层上，其中第一应力层的边缘与第二蚀刻停止层的边缘对准; 第二应力层，设置在所述第二晶体管上; 以及设置在所述第二晶体管和所述第二应力层上的第三蚀刻停止层，其中所述第二应力层的边缘与所述第三蚀刻停止层的边缘对准。