Abstract:
A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use. The overall IC manufacture would have an increased yield as compared to the prior art.
Abstract:
A repairable memory module, such as a DRAM (dynamic random access memory) or a flash memory module, and a method of repairing memory modules are proposed. Based on the repairable memory module, any failed memory ICs in the module that are found before shipment or after use can be repaired through the use of a backup memory IC. Fundamentally, when any failed memory ICs are found in the module, a set of zero-ohm resistors are used to short-circuit a number of selected pairs of jumping pads to thereby redirect the connections to the I/O (input/output) and column-address strobe pins on the failed memory IC instead to the same nominal pins on the backup memory IC. This allows the function of the failed ICs to be instead performed by the backup memory chip.