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    Three dimensional geometrical puzzle
    1.
    发明申请
    Three dimensional geometrical puzzle 审中-公开
    三维几何拼图

    公开(公告)号：US20060061033A1

    公开(公告)日：2006-03-23

    申请号：US10947452

    申请日：2004-09-22

    Applicant: Charlie Han

    Inventor： Charlie Han

    IPC: A63F9/08

    CPC classification number: A63F9/083 ,  A63F9/0857 ,  A63F2009/0815 ,  A63F2009/0888

    Abstract: A handheld puzzle is described. The puzzle reduces friction between moveable pieces and at the same time allows for restrained alignment of the moveable pieces. An inner core of the puzzle can be adapted for use with a plurality of outer moveable face pieces that can comprise a variety of surface geometries.

    Abstract translation: 描述了一个手持谜题。 该益智减少可移动件之间的摩擦，同时允许可移动件的限制对准。 拼图的内芯可以适用于可以包括各种表面几何形状的多个外部可移动的面部件。

    Preburn-in dynamic random access memory module and preburn-in circuit board thereof
    4.
    发明授权
    Preburn-in dynamic random access memory module and preburn-in circuit board thereof 失效
    Preburn-in动态随机存取存储器模块及其Preburn-in电路板

    公开(公告)号：US06279141B1

    公开(公告)日：2001-08-21

    申请号：US09434987

    申请日：1997-08-13

    Applicant: Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    Inventor： Min-Chih Hsuan ,  Charlie Han ,  Jerry Jaw ,  Tung-Chi Liu

    IPC: G06F1750

    CPC classification number: G11C29/56016 ,  G11C11/401 ,  G11C29/48 ,  H05K1/0286 ,  H05K3/0052

    Abstract: A preburn-in DRAM module circuit board is provided, which allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked. After the burn-in process, each of the DRAM modules can be cut apart from the circuit board to serve as a single memory module. The preburn-in DRAM module circuit board allows the manufacturing process for the DRAM modules to be reduced in schedule and manufacturing cost. Material cost can also be saved since the burn-in circuit and the module circuit are arranged on the same circuit board.

    Abstract translation: 提供了一种预烧入式DRAM模块电路板，其允许在其上直接构建多个DRAM模块，并且其可以直接连接到大型老化炉，以便在DRAM上同时执行老化过程 安装在其上的模块，以检查要重新加工的任何缺陷的IC芯片。 在老化过程之后，可以将每个DRAM模块与电路板分开以用作单个存储器模块。 预烧入式DRAM模块电路板允许在时间表和制造成本上减少DRAM模块的制造过程。 由于老化电路和模块电路布置在同一电路板上，因此也可节省材料成本。

    Wafer level integrated circuit structure and method of manufacturing the same
    5.
    发明授权
    Wafer level integrated circuit structure and method of manufacturing the same 有权
    晶圆级集成电路结构及其制造方法

    公开(公告)号：US06214630B1

    公开(公告)日：2001-04-10

    申请号：US09471059

    申请日：1999-12-22

    Applicant: Min-Chih Hsuan ,  Taisheng Feng ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Taisheng Feng ,  Charlie Han

    IPC: H01L2100

    CPC classification number: H01L22/22 ,  G01R31/318505 ,  G01R31/318511 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wafer level IC structure and a method of manufacturing this wafer level IC structure are proposed, which can help increase the yield of the IC manufacture. The wafer level IC structure is constructed on a semiconductor wafer which is defined into a plurality of discrete IC blocks on the wafer, each IC block being used to form a plurality of IC components such as memory cells. A multi-layer interconnect structure is formed to electrically interconnect these IC components in each of the IC blocks. A first testing and repair process is then perform to disconnect any inoperative IC components from active use. This completes the fabrication stage of the manufacture process. In the subsequent packaging stage, a redistribution line structure is formed to interconnect the discrete IC blocks into an integral functional unit. A second testing and repair process is then perform to disconnect any inoperative IC blocks from active use. The overall IC manufacture would have an increased yield as compared to the prior art.

    Abstract translation: 提出了晶片级IC结构和制造该晶片级IC结构的方法，这有助于提高IC制造的成品率。 晶片级IC结构构造在半导体晶片上，半导体晶片被限定在晶片上的多个分立IC块中，每个IC块用于形成诸如存储单元的多个IC部件。 形成多层互连结构以将每个IC块中的这些IC部件电连接。 然后执行第一个测试和修复过程，以断开任何不起作用的IC组件的主动使用。 这完成了制造过程的制造阶段。 在随后的封装阶段中，形成再分配线结构以将分立IC块互连成为一体的功能单元。 然后执行第二个测试和修复过程以断开任何不工作的IC块与主动使用。 与现有技术相比，整体IC制造将具有增加的产量。

    Repairable memory module and method of repairing memory modules
    6.
    发明授权
    Repairable memory module and method of repairing memory modules 失效
    可修复的内存模块和修复内存模块的方法

    公开(公告)号：US5875136A

    公开(公告)日：1999-02-23

    申请号：US907642

    申请日：1997-08-11

    Applicant: Min-Chih Hsuan ,  Jerry Jaw ,  Charlie Han

    Inventor： Min-Chih Hsuan ,  Jerry Jaw ,  Charlie Han

    IPC: G11C5/06

    CPC classification number: G11C29/81 ,  G11C29/808 ,  G11C29/816 ,  G11C5/04

    Abstract: A repairable memory module, such as a DRAM (dynamic random access memory) or a flash memory module, and a method of repairing memory modules are proposed. Based on the repairable memory module, any failed memory ICs in the module that are found before shipment or after use can be repaired through the use of a backup memory IC. Fundamentally, when any failed memory ICs are found in the module, a set of zero-ohm resistors are used to short-circuit a number of selected pairs of jumping pads to thereby redirect the connections to the I/O (input/output) and column-address strobe pins on the failed memory IC instead to the same nominal pins on the backup memory IC. This allows the function of the failed ICs to be instead performed by the backup memory chip.

    Abstract translation: 提出了诸如DRAM（动态随机存取存储器）或闪速存储器模块的可修复存储器模块以及修复存储器模块的方法。 基于可修复的存储器模块，可以通过使用备用存储器IC来修复在发货之前或使用后发现的模块中的任何故障存储器IC。 基本上，当在模块中发现任何失败的存储器IC时，使用一组零欧姆电阻器来使多个选定跳跃焊盘对短路，从而将连接重定向到I / O（输入/输出）和 故障存储器IC上的列地址选通引脚替代为备用存储器IC上的相同标称引脚。 这允许由备用存储器芯片替代执行故障IC的功能。

    Dual-dies packaging structure and packaging method
    7.
    发明授权
    Dual-dies packaging structure and packaging method 有权
    双模包装结构和包装方法

    公开(公告)号：US06399421B2

    公开(公告)日：2002-06-04

    申请号：US09797546

    申请日：2001-03-01

    Applicant: Charlie Han ,  Te-Sheng Yang

    Inventor： Charlie Han ,  Te-Sheng Yang

    IPC: H01L2144

    CPC classification number: H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

    Abstract translation: 提供了双模封装结构。 双模封装结构包括引线框架，引线框架还包括管芯焊盘和多个引脚，其中管芯焊盘包括上表面和下表面。 具有多个第一接合焊盘的第一管芯通过例如胶合而固定在管芯焊盘的上表面上。 第一个焊盘保持暴露。 具有多个第二接合焊盘的第二管芯通过例如胶合而固定在下表面上。 第二个焊盘保持暴露。 凸起再分配结构层位于第二管芯上，以将每个第二接合焊盘重新分布到伪接合焊盘。 每个伪焊盘相对于第一焊盘具有适当的位置。 因此，当使用多个接合线将第一接合焊盘和伪接合焊盘接合到引线脚时，可以规则地且简单地接合接合线而不会彼此交叉或缠结。

    Dual-dies packaging structure and packaging method
    9.
    发明授权
    Dual-dies packaging structure and packaging method 有权
    双模包装结构和包装方法

    公开(公告)号：US06313527B1

    公开(公告)日：2001-11-06

    申请号：US09210270

    申请日：1998-12-10

    Applicant: Charlie Han ,  Te-Sheng Yang

    Inventor： Charlie Han ,  Te-Sheng Yang

    IPC: H01L2334

    CPC classification number: H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

    Abstract translation: 提供了双模封装结构。 双模封装结构包括引线框架，引线框架还包括管芯焊盘和多个引脚，其中管芯焊盘包括上表面和下表面。 具有多个第一接合焊盘的第一管芯通过例如胶合而固定在管芯焊盘的上表面上。 第一个焊盘保持暴露。 具有多个第二接合焊盘的第二管芯通过例如胶合而固定在下表面上。 第二个焊盘保持暴露。 凸起再分配结构层位于第二管芯上，以将每个第二接合焊盘重新分布到伪接合焊盘。 每个伪焊盘相对于第一焊盘具有适当的位置。 因此，当使用多个接合线将第一接合焊盘和伪接合焊盘接合到引线脚时，可以规则地且简单地接合接合线而不会彼此交叉或缠结。

    Method for determining failure rate and selecting best burn-in time
    10.
    发明授权
    Method for determining failure rate and selecting best burn-in time 有权
    确定故障率并选择最佳老化时间的方法

    公开(公告)号：US06820029B2

    公开(公告)日：2004-11-16

    申请号：US09742224

    申请日：2000-12-22

    Applicant: Walx Fang ,  Charlie Han

    Inventor： Walx Fang ,  Charlie Han

    IPC: H01L2166

    CPC classification number: G01R31/30

    Abstract: A method for determining failure rate and selecting a best burn-in time is disclosed. The method comprises the following steps. First of all, integrate circuits are provided. Then a life-time testing process is performed, wherein a failure rate versus testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, wherein an acceleration factor function also is established under the testing environment. Next a simulating process that uses a testing time function is performed to simulate the failure rate versus testing time relation. Then a transforming process that uses the acceleration factor function is performed to transform the testing time function into a real time function. Finally, an integrating process is performed to integrate the real time function through a calculating region to acquire an accumulated failure rate real time function.

    Abstract translation: 公开了一种确定故障率并选择最佳老化时间的方法。 该方法包括以下步骤。 首先提供集成电路。 然后进行终身测试过程，其中通过测量测试环境下的每个集成电路的寿命来建立故障率与测试时间关系，其中在测试环境下也建立加速因子函数。 接下来，使用使用测试时间功能的模拟过程来模拟故障率与测试时间关系。 然后执行使用加速因子函数的变换过程，以将测试时间函数转换为实时函数。 最后，进行积分处理，通过计算区域对实时功能进行积分，以获取累积的故障率实时功能。

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