Abstract:
A system and method for providing memory bandwidth efficient correlation acceleration. A correlation accelerator or correlator (e.g., an X*Y correlator) can be configured in association with a processor of a wireless communication system for correlating an input signal data sequence (X) and its shifted versions with a reference data sequence. Shifted versions (including the 0-shifted or the original) with respect to the input signal data sequence can be generated for each column (Y columns) of a sliding window in the correlator in order to reduce an input bandwidth requirement. Each input signal data and the shifted versions can be concurrently multiplied with the reference signal data and the results can be summed together in order to generate an output signal data profile. The output signal data profile can be stored into an accumulator register in order to reduce an output bandwidth requirement.
Abstract:
A vehicle transmission is adapted to transmit a power output from an engine unit to a wheel. The vehicle transmission includes a driving unit and a speed-changing unit. The driving unit includes a main box, a first driving mechanism disposed within the main box and adapted to be driven by the engine unit, and an output shaft driven by the first driving mechanism. The speed-changing unit includes an auxiliary box connected removably to the main box, a second driving mechanism disposed within the auxiliary box and driven by the output shaft, and an axle parallel to the output shaft and driven by the second driving mechanism. The axle is connected fixedly to the wheel, and extends into the auxiliary box.
Abstract:
A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.