公开(公告)号：US08384276B2

公开(公告)日：2013-02-26

申请号：US13167704

申请日：2011-06-24

Applicant: Min-Tsun Hsieh ,  Wen-Liang Tseng ,  Lung-Hsin Chen ,  Chih-Yung Lin ,  Ching-Lien Yeh

Inventor： Min-Tsun Hsieh ,  Wen-Liang Tseng ,  Lung-Hsin Chen ,  Chih-Yung Lin ,  Ching-Lien Yeh

IPC: H01J1/02

CPC classification number: F21V29/004 ,  F21K9/233 ,  F21V7/0083 ,  F21V13/04 ,  F21V17/102 ,  F21V29/773 ,  F21Y2105/10 ,  F21Y2115/10

Abstract: An LED lamp structure includes a heat sink and a base. The heat sink includes a first receiving cavity, a second receiving cavity opposite to the first receiving cavity and a partition. A light board having LED modules is mounted on the partition. The partition defines two first threaded through holes therein. The base has two positioning protrusions engaging in two positioning grooves of the heat sink. Thus, second screw holes of two screw pillars of the base are aligned at the first screw holes of the partition of the heat sink. Screws are used to threadedly engage in the first screw holes, the second screw holes and third screw holes in the light board to thereby assemble the heat sink, the base and the light board together.

Abstract translation: LED灯结构包括散热器和基座。 散热器包括第一接收腔，与第一接收腔相对的第二接收腔和隔板。 具有LED模块的灯板安装在隔板上。 隔板在其中限定了两个第一螺纹通孔。 基座具有两个定位突起，该突起与散热器的两个定位槽啮合。 因此，基座的两个螺柱的第二螺钉孔在散热器的隔板的第一螺钉孔处对准。 螺丝用于螺纹接合灯板中的第一螺钉孔，第二螺钉孔和第三螺钉孔，从而将散热器，基座和灯板组装在一起。

公开(公告)号：USD654444S1

公开(公告)日：2012-02-21

申请号：US29380581

申请日：2010-12-08

Applicant: Chih-Yung Lin ,  Min-Tsun Hsieh ,  Ching-Lien Yeh ,  Lung-Hsin Chen ,  Wen-Liang Tseng

Designer： Chih-Yung Lin ,  Min-Tsun Hsieh ,  Ching-Lien Yeh ,  Lung-Hsin Chen ,  Wen-Liang Tseng

公开(公告)号：US06548226B2

公开(公告)日：2003-04-15

申请号：US09780551

申请日：2001-02-09

Applicant: Chih-Yung Lin

Inventor： Chih-Yung Lin

IPC: G03F700

CPC classification number: G03F7/0045

Abstract: A photolithographic process for patterning a photoresist layer over a substrate. A positive photoresist layer is formed over the substrate. The positive photoresist layer contains a photoacid generator and a photobase generator. The positive photoresist layer is exposed to light through a photomask so that the photoacid generator in the photoresist layer is changed into photoacid and the photobase generator is changed to photobase. The photomask has a first pattern region and a second pattern region that correspond with a first region and a second region of the photoresist layer. The first pattern region has a duty ratio greater than the second pattern region so that the first region is exposed to a higher light intensity than the second region. Finally, the positive photoresist layer is developed. The reaction threshold for turning the photobase generator into photobase is adjusted according to the exposure strength between the first region and the second region. Therefore, the quantity of photobase generated in the first region is much greater than in the second region. Ultimately, the diffusion of photoacid within the first region is blocked without affecting the development of the positive photoresist layer in the second region.

公开(公告)号：US06365468B1

公开(公告)日：2002-04-02

申请号：US09598192

申请日：2000-06-21

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Chih-Yung Lin

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Chih-Yung Lin

IPC: H01L21336

CPC classification number: H01L21/823835 ,  H01L21/2807 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region. A source/drain region is formed into the semiconductor substrate. The silicon nitride layer is removed. Finally, salicide region is formed into the source/drain region and upon the surface of silcion layer to complete the silicon gate structure.

Abstract translation: 公开了用于形成掺杂p型栅极的方法，如以下描述。 该方法包括：首先提供半导体衬底。 蚀刻半导体衬底以形成作为浅沟槽隔离的凹部。 将第一个二氧化硅填充到浅沟槽隔离中。 n型阱形成在半导体衬底中。 在半导体衬底的表面和浅沟槽隔离的表面上形成被称为掺杂p型层的硅锗层。 在硅锗层的表面上形成称为抗反射层的氮化硅层。 蚀刻氮化硅层的部分和硅锗层的部分作为栅极区域。 源/漏扩展形成。 在半导体衬底的表面和氮化物层的表面上沉积第二二氧化硅层。 将第二二氧化硅层作为栅极区域的侧壁旁边的间隔物进行蚀刻。 源极/漏极区域形成为半导体衬底。 去除氮化硅层。 最后，将硅化物区域形成为源极/漏极区域，并在硅酸盐层的表面形成硅栅极结构。

公开(公告)号：US06348301B1

公开(公告)日：2002-02-19

申请号：US09427793

申请日：1999-10-27

Applicant: Chih-Yung Lin

Inventor： Chih-Yung Lin

IPC: G03F740

CPC classification number: G03F7/40

Abstract: A method of lowering critical dimensions. A film layer and a photoresist layer are sequentially formed over a substrate. The photoresist layer is exposed and developed to form a plurality of first openings. A first baking of the photoresist layer is carried out, permitting the photoresist layer to flow. A second baking is next carried out so that the width of the first openings is reduced linearly with time until a desired dimension is reached. Using the photoresist layer as a mask, the film layer is etched to form a plurality of second openings.

Abstract translation: 降低关键尺寸的方法。 在衬底上依次形成膜层和光致抗蚀剂层。 光致抗蚀剂层被曝光和显影以形成多个第一开口。 进行光致抗蚀剂层的第一次烘烤，允许光致抗蚀剂层流动。 接下来进行第二烘烤，使得第一开口的宽度随着时间线性地减小直到达到期望的尺寸。 使用光致抗蚀剂层作为掩模，蚀刻膜层以形成多个第二开口。

公开(公告)号：US06294834B1

公开(公告)日：2001-09-25

申请号：US09514217

申请日：2000-02-25

Applicant: Wen-Kuan Yeh ,  Chih-Yung Lin

Inventor： Wen-Kuan Yeh ,  Chih-Yung Lin

IPC: H01L2940

CPC classification number: H01L28/10 ,  H01L23/4825 ,  H01L27/1203 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure of combined passive elements and logic circuits on a SOI (Silicon On Insulator) wafer. By combining passive elements (including a resistor, an inductor and a capacitor) with a logic device on a SOI wafer with dual damascene technology, an extremely thick inductor that effectively reduces the resistance of the inductor can be formed while also reducing the layout area. The invention is compatible with conventional VLSI technology without increasing number of masks or process steps. Furthermore, because the resistor of the invention is composed of single crystal Si, the resistor has high stability and low noise. Therefore, the structure according to the invention is suitable for RF device design and is also suitable for a System On Chip design.

Abstract translation: SOI（绝缘体上硅）晶片上的无源元件和逻辑电路的组合。 通过将无源元件（包括电阻器，电感器和电容器）与具有双镶嵌技术的SOI晶片上的逻辑器件相结合，可以形成有效降低电感器电阻的极厚电感器，同时也减少了布局面积。 本发明与常规VLSI技术兼容，而不增加掩模或工艺步骤的数量。 此外，由于本发明的电阻器由单晶硅构成，所以电阻器的稳定性高，噪音低。 因此，根据本发明的结构适用于RF器件设计，并且也适用于片上系统设计。