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65 条记录 (耗时 0.04 秒)

    CDM ESD event protection in application circuits
    21.
    发明授权
    CDM ESD event protection in application circuits 失效
    应用电路中的CDM ESD事件保护

    公开(公告)号：US07493576B2

    公开(公告)日：2009-02-17

    申请号：US11349356

    申请日：2006-02-07

    申请人： William Loh ,  Li Lynn Ooi ,  Choshu Ito

    发明人： William Loh ,  Li Lynn Ooi ,  Choshu Ito

    IPC分类号： G06F17/50 ,  G06F9/00

    CPC分类号： G06F17/5036

    摘要： Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

    摘要翻译： 改进设计修复的方法和结构，以前由于CDM ESD事件引起的应用电路设计的核心电路的莫名其妙的损害。 本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。 其特征和方面自动改变应用电路设计，以通过各种技术提供补救以减少这种电感耦合的幅度，从而降低应用电路对CDM ESD事件的损害的敏感性。 在应用电路的初始设计期间，修改可以被执行为规则，或者作为响应于模拟的设计的重新配置以发现设计中的不适当的耦合。

    CDM ESD event simulation and remediation thereof in application circuits
    22.
    发明授权
    CDM ESD event simulation and remediation thereof in application circuits 失效
    CDM ESD事件模拟及其在应用电路中的修复

    公开(公告)号：US07458044B2

    公开(公告)日：2008-11-25

    申请号：US11349358

    申请日：2006-02-07

    申请人： Choshu Ito ,  Li Lynn Ooi ,  William Loh

    发明人： Choshu Ito ,  Li Lynn Ooi ,  William Loh

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5036

    摘要： Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.

    摘要翻译： 改进CDM ESD事件仿真和修复电路设计的方法和结构，以纠正由此类事件引起的应用电路设计对核心电路的以前不可思议的损害。 本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。 根据其特征和方面的改进的仿真技术可以预测这种感应耦合可能会对核心电路造成损害。 本发明的其它特征和方面可以改变应用电路设计，以通过将附加的缓冲电路自动插入到可能受这种电感耦合影响的核心电路的芯线迹来提供补救。

    Row based analog standard cell layout design and methodology
    23.
    发明授权
    Row based analog standard cell layout design and methodology 有权
    基于行的模拟标准单元布局设计和方法

    公开(公告)号：US09292644B2

    公开(公告)日：2016-03-22

    申请号：US13572697

    申请日：2012-08-13

    申请人： William Loh ,  Erik Vaclav Chmelar

    发明人： William Loh ,  Erik Vaclav Chmelar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5063

    摘要： A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.

    摘要翻译： 一种设计SoC的物理布局的系统和方法，该SoC包括将高度限制在其预定行高度或整数倍的模拟标准单元的基于行的放置。 模拟标准单元库可以被ECAD工具利用，以类似于这样的ECAD工具可以利用数字标准单元库来映射，放置和路由数字地图，放置和路由数字地图，放置和路由模拟和混合信号电路 电路。 数字，模拟和混合信号电路的映射，放置和布线可以在统一的ECAD SoC物理设计流程中进行。 最后，教授了通用型模拟标准单元，以进一步提高模拟和混合信号SoC布局的速度和效率。

    2-(1-(5-Halothienylmethoxyimino) ethyl-3-hydroxy-5-(tetrahydro-2H-thiopyranyl)-cyclohex-2-en-1-one herbicides
    30.
    发明授权
    2-(1-(5-Halothienylmethoxyimino) ethyl-3-hydroxy-5-(tetrahydro-2H-thiopyranyl)-cyclohex-2-en-1-one herbicides 失效
    2-（1-（5-卤代噻吩基甲氧基亚氨基）乙基-3-羟基-5-（四氢-2H-噻喃基） - 环己-2-烯-1-酮除草剂

    公开(公告)号：US4824470A

    公开(公告)日：1989-04-25

    申请号：US101321

    申请日：1987-09-25

    申请人： William Loh

    发明人： William Loh

    IPC分类号： A01N43/18 ,  C07D409/12 ,  C07D409/02 ,  A01N43/02

    CPC分类号： C07D409/12 ,  A01N43/18

    摘要： 2-[1-[(5-chlorothien-2-yl)methoxyimino]ethyl]-3-hydroxy-5- (tetrahydro-2H-thiopyran-3-yl)-cyclohex-2-en-1-one and 3-alkanoyloxy thereof derivatives are disclosed. The compounds exhibit pre- and post-emergent phytotoxicity and are useful as selective post-emergent herbicides against grasses.

    摘要翻译： 2- [1 - [（5-氯噻吩-2-基）甲氧基亚氨基]乙基] -3-羟基-5-（四氢-2H-噻喃-3-基） - 环己-2-烯-1-酮和3- 其烷酰氧基衍生物被公开。 这些化合物显示出芽前和出苗后的植物毒性，可用作抗草药的选择性芽后除草剂。