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公开(公告)号：US07034729B2
公开(公告)日：2006-04-25
申请号：US10935675
申请日：2004-09-02
IPC分类号： H03M3/00
CPC分类号： H03K5/249
摘要： An adding circuit includes storage capacitors and a a switch mechanism, the storage capacitors being charged up via voltage signals to be added during a first clock phase. During a second clock phase, the storage capacitors are connected in parallel, with the result that a charge equalization occurs. After the charge equalization, the voltage dropped across the parallel-connected storage capacitors is equal to a sum of the signals to be added except for a scaling factor. In one embodiment, the adding circuit is used in a sigma-delta modulator circuit.
摘要翻译： 加法电路包括存储电容器和开关机构，存储电容器通过在第一时钟相位期间被添加的电压信号而被充电。 在第二时钟相位期间，存储电容器并联连接，结果是发生电荷均衡。 在电荷均衡之后，并联连接的存储电容器中的电压下降等于除了缩放因子之外要添加的信号的总和。 在一个实施例中，加法电路用于Σ-Δ调制器电路。
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公开(公告)号：US20050156654A1
公开(公告)日：2005-07-21
申请号：US11009538
申请日：2004-12-10
申请人： Richard Gaggl , Joerg Hauptmann
发明人： Richard Gaggl , Joerg Hauptmann
IPC分类号： H03H19/00 , A61K31/553
CPC分类号： H03H19/004
摘要： The invention relates to a linear SC circuit arrangement using integrated deep submicron technology, having at least one switched capacitor circuit which is connected to an input for inputting an input signal and which has at least one switchable capacitor and at least one first transistor, having a control circuit for directly actuating the first transistors, having an output stage which has second transistors and which is arranged downstream of the switched capacitor circuit, where the first transistors are in the form of thick oxide transistors and have a higher withstand voltage than the second transistors.
摘要翻译： 本发明涉及使用集成深亚微米技术的线性SC电路装置，其具有至少一个开关电容器电路，其连接到用于输入输入信号的输入端，并且具有至少一个可切换电容器和至少一个第一晶体管，该第一晶体管具有 用于直接致动第一晶体管的控制电路，具有具有第二晶体管并且布置在开关电容器电路的下游的输出级，其中第一晶体管是厚氧化物晶体管的形式并且具有比第二晶体管更高的耐受电压 。
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公开(公告)号：US20050093728A1
公开(公告)日：2005-05-05
申请号：US10935675
申请日：2004-09-02
CPC分类号： H03K5/249
摘要： An adding circuit is disclosed. The adding circuit includes storage capacitors and switching or switching means, the storage capacitors being charged up via voltage signals to be added during a first clock phase. During a second clock phase, the storage capacitors are connected in parallel, with the result that a charge equalization occurs. After the charge equalization, the voltage dropped across the parallel-connected storage capacitors is equal to a sum of the signals to be added except for a scaling factor. In one embodiment, the adding circuit is used in a sigma-delta modulator circuit.
摘要翻译： 公开了一种加法电路。 加法电路包括存储电容器和开关或开关装置，存储电容器通过在第一时钟相位期间被加到的电压信号进行充电。 在第二时钟相位期间，存储电容器并联连接，结果是发生电荷均衡。 在电荷均衡之后，并联连接的存储电容器中的电压下降等于除了缩放因子之外要添加的信号的总和。 在一个实施例中，加法电路用于Σ-Δ调制器电路。
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公开(公告)号：US06738002B2
公开(公告)日：2004-05-18
申请号：US10229936
申请日：2002-08-28
IPC分类号： H03M120
摘要： A sigma-delta analog-to-digital converter includes an integrator and a dither signal generator for generating a digital dither signal, and a plurality of comparators for converting an analog signal received from the integrator into an output digital value. A digital logic unit is in data communication with the digital dither signal and the comparators. The digital logic unit is configured to change the output digital value on the basis of the digital dither signal.
摘要翻译： Σ-Δ模数转换器包括用于产生数字抖动信号的积分器和抖动信号发生器，以及用于将从积分器接收的模拟信号转换为输出数字值的多个比较器。 数字逻辑单元与数字抖动信号和比较器进行数据通信。 数字逻辑单元被配置为基于数字抖动信号来改变输出数字值。
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