公开(公告)号：US07050348B2

公开(公告)日：2006-05-23

申请号：US10880343

申请日：2004-06-29

Applicant: Christophe Frey ,  Franck Genevaux

Inventor： Christophe Frey ,  Franck Genevaux

IPC: G11C7/00

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C2207/065

Abstract: An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.

Abstract translation: 集成电路包括存储器，并且存储器包括以行和列排列的存储器平面以及连接到存储器平面的列的多个读取放大器。 参考路径包括第一参考列和第二参考列，并且参考存储单元连接在第一和第二参考列之间。 参考行连接到参考存储单元以供选择，使得第一参考列导通放电电流，而第二参考列导通漏电流。 控制电路连接在第一和第二参考列和读取放大器之间。 当第一和第二参考列上的电压之间的绝对值超过阈值时，控制电路向读取放大器提供激活信号。

公开(公告)号：US20060002186A1

公开(公告)日：2006-01-05

申请号：US10881747

申请日：2004-06-30

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C11/15

CPC classification number: G11C14/0081 ,  G11C11/16

Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

公开(公告)号：US06678184B2

公开(公告)日：2004-01-13

申请号：US10163848

申请日：2002-06-05

Applicant: Mark A. Lysinger ,  Christophe Frey ,  Frederic LaLanne

Inventor： Mark A. Lysinger ,  Christophe Frey ,  Frederic LaLanne

IPC: G11C1500

CPC classification number: G11C15/04

Abstract: A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

Abstract translation: 公开了具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。 六个晶体管的比较电路形成在两个有源区域上。 比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。 比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。

公开(公告)号：US06430720B1

公开(公告)日：2002-08-06

申请号：US09103189

申请日：1998-06-23

Applicant: Christophe Frey ,  Stéphane Hanriat

Inventor： Christophe Frey ,  Stéphane Hanriat

IPC: G01R3128

CPC classification number: G01R31/318536 ,  G01R31/318552

Abstract: The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being synchronized by an external clock signal; serially providing of this test pattern to an input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal; storing, in a second test register connected to the output of the internal logic circuit, at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storing being synchronized by the test clock signal; and providing to the outside, by series shifting, of the resulting pattern, this providing step being synchronized by the external clock signal.

Abstract translation: 本发明涉及逻辑电路的功能测试方法和实现该方法的集成电路。 该方法包括在第一测试寄存器中提供至少一个测试模式和该测试模式的存储，该提供步骤由外部时钟信号同步; 将该测试模式串行地提供给内部逻辑电路的输入，该提供步骤由从内部时钟信号产生的测试时钟信号同步; 在连接到内部逻辑电路的输出的第二测试寄存器中存储当测试图案被提供给内部逻辑电路时产生的至少一个所得到的模式，该存储由测试时钟信号同步; 并通过串行移位向外部提供所得图案，该提供步骤由外部时钟信号同步。

公开(公告)号：US06314041B1

公开(公告)日：2001-11-06

申请号：US09553638

申请日：2000-04-20

Applicant: Christophe Frey

Inventor： Christophe Frey

IPC: G11C700

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at least one MOS transistor a turn-off control signal to enter a stand-by mode, whereby the overall resistance of the column and of the at least one transistor increases in stand-by mode.

Abstract translation: 包括存储器单元线和列阵列的SRAM，每列在高电源电压和低电源电压之间提供，所述高电源电压和低电源电压包括与每列串联的至少一个MOS晶体管，以及用于施加到所述至少一个MOS的电路 晶体管关断控制信号进入待机模式，由此在待机模式下，列和至少一个晶体管的整体电阻增加。