公开(公告)号：US20050080995A1

公开(公告)日：2005-04-14

申请号：US10685054

申请日：2003-10-14

申请人： Gordon Davis ,  Thomas Genduso

发明人： Gordon Davis ,  Thomas Genduso

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/126

摘要： A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

摘要翻译： 一种用于提高缓存性能的方法和系统。 缓存可以包括标识条目，其标识由数据未位于高速缓存中的处理器先前请求的地址。 如果处理器第二次请求该地址，则重新有可能再次访问该地址。 当处理器第二次请求由标签条目标识的地址时，通过插入位于该地址的数据并驱逐位于最近最少使用的条目中的数据来更新高速缓存。 以这种方式，除非存在可能再次访问缓存中的数据的重大概率，否则数据将不会从高速缓存中逐出。 因此，数据可能不会被处理器在高速缓存中驱逐，并且被替换为不被重用的数据，例如在中断程序中。

公开(公告)号：US20080010390A1

公开(公告)日：2008-01-10

申请号：US11856509

申请日：2007-09-17

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

公开(公告)号：US20070079106A1

公开(公告)日：2007-04-05

申请号：US11232773

申请日：2005-09-22

申请人： Gordon Davis

发明人： Gordon Davis

IPC分类号： G06F12/00 ,  G06F7/00

CPC分类号： G06F12/1018 ,  G06F2212/1044

摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

摘要翻译： 页表机制将虚拟地址转换为实际地址。 在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。 优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。 在第二方面，虚拟地址索引二进制树定义结构。 解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。

公开(公告)号：US20070033303A1

公开(公告)日：2007-02-08

申请号：US11198042

申请日：2005-08-05

申请人： Jeffrey Bridges ,  Gordon Davis ,  Thomas Sartorius ,  Michael Siegel

发明人： Jeffrey Bridges ,  Gordon Davis ,  Thomas Sartorius ,  Michael Siegel

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

公开(公告)号：US20080098015A1

公开(公告)日：2008-04-24

申请号：US11962558

申请日：2007-12-21

申请人： Gordon Davis ,  Andreas Herkersdorf ,  Clark Jeffries ,  Mark Rinaldi

发明人： Gordon Davis ,  Andreas Herkersdorf ,  Clark Jeffries ,  Mark Rinaldi

IPC分类号： G06F17/30

CPC分类号： H04L49/3009 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/351

摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

摘要翻译： 一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制键的冲突。 不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。 如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。 如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

公开(公告)号：US20080052486A1

公开(公告)日：2008-02-28

申请号：US11930513

申请日：2007-10-31

申请人： Gordon Davis

发明人： Gordon Davis

IPC分类号： G06F12/00

CPC分类号： G06F12/1018 ,  G06F2212/1044

摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

摘要翻译： 页表机制将虚拟地址转换为实际地址。 在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。 优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。 在第二方面，虚拟地址索引二进制树定义结构。 解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。

公开(公告)号：US20080028140A1

公开(公告)日：2008-01-31

申请号：US11867963

申请日：2007-10-05

申请人： Gordon Davis ,  Andreas Herkersdorf ,  Clark Jeffries ,  Mark Rinaldi

发明人： Gordon Davis ,  Andreas Herkersdorf ,  Clark Jeffries ,  Mark Rinaldi

IPC分类号： G06F12/00

CPC分类号： H04L49/3009 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/351

摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

摘要翻译： 一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制密钥的冲突。 不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。 如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。 如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

公开(公告)号：US20060209898A1

公开(公告)日：2006-09-21

申请号：US11348417

申请日：2006-02-07

申请人： Youssef Abdelilah ,  Gordon Davis ,  Jeffrey Derby ,  Dongming Hwang ,  Clark Jeffries ,  Malcolm Ware ,  Hua Ye

发明人： Youssef Abdelilah ,  Gordon Davis ,  Jeffrey Derby ,  Dongming Hwang ,  Clark Jeffries ,  Malcolm Ware ,  Hua Ye

IPC分类号： H04J3/18

CPC分类号： H04L47/10 ,  H04L12/6418 ,  H04L29/06027 ,  H04L47/12 ,  H04L47/2425 ,  H04L47/263 ,  H04L47/70 ,  H04L47/745 ,  H04L47/748 ,  H04L47/762 ,  H04L65/1009 ,  H04L65/607 ,  H04L65/80 ,  H04L2012/6481 ,  H04L2012/6497

摘要： A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network. As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.

摘要翻译： 编解码器检测分组网络中的拥塞，并通过会话控制协议进行响应，以使用接收编解码器重新协商编解码器类型和/或参数，以减少支持会话的比特率。 一旦建立了连接和会话，编码的数据包将在两个编解码器之间开始流动。 控制实体在会话中定期发送和接收网络拥塞控制报文。 拥塞控制分组向接收编解码器提供“心跳”信号。 当网络不拥塞时，所有“心跳”数据包将通过网络传递。 随着网络拥塞的增加，网络内的路由器丢弃多余的数据包，防止网络故障。 编解码器通过减慢比特率或通过会话控制协议进行重新协商较低的比特率来响应丢失的分组。 如果没有丢失数据包，则编解码器检测会话是否以最高比特率运行，如果不是，则重新协商更高的比特率。

公开(公告)号：US20060020600A1

公开(公告)日：2006-01-26

申请号：US10894628

申请日：2004-07-20

申请人： Everett Corl ,  Gordon Davis ,  Clark Jeffries

发明人： Everett Corl ,  Gordon Davis ,  Clark Jeffries

IPC分类号： G06F17/30

CPC分类号： H04L43/16 ,  H04L43/18 ,  H04L49/25 ,  H04L63/0263

摘要： The present invention relates to a method and computer system device for applying a plurality of rules to data packets within a network computer system. A filter rule decision tree is updated by adding or deleting a rule. If deleting a filter rule then the decision tree is provided to a network data plane processor with an incremental delete of the filter rule. If adding a filter rule then either providing an incremental insertion of the filter rule to the decision tree or rebuilding the first decision tree into a second decision tree responsive to comparing a parameter to a threshold. In one embodiment the parameter and thresholds relate to depth values of the tree filter rule chained branches. In another the parameter and thresholds relate to a total count of rule additions since a building of the relevant tree.

公开(公告)号：US20050185581A1

公开(公告)日：2005-08-25

申请号：US10782617

申请日：2004-02-19

申请人： Jeffrey Bradford ,  Gordon Davis ,  Dongming Hwang ,  Clark Jeffries ,  Srinivasan Ramani ,  Kartik Sudeep ,  Ken Vu

发明人： Jeffrey Bradford ,  Gordon Davis ,  Dongming Hwang ,  Clark Jeffries ,  Srinivasan Ramani ,  Kartik Sudeep ,  Ken Vu

IPC分类号： H04L12/56 ,  H04J3/16

CPC分类号： H04L47/10 ,  H04L47/29 ,  H04L47/323

摘要： The present invention provides for a computer network method and system that applies “hysteresis” to an active queue management algorithm. If a queue is at a level below a certain low threshold and a burst of packets arrives at a network node, then the probability of dropping the initial packets in the burst is recalculated, but the packets are not dropped. However, if the queue level crosses beyond a hysteresis threshold, then packets are discarded pursuant to a drop probability. Also, according to the present invention, queue level may be decreased until it becomes less than the hysteresis threshold, with packets dropped per the drop probability until the queue level decreases to at least a low threshold. In one embodiment, an adaptive algorithm is also provided to adjust the transmit probability for each flow together with hysteresis to increase the packet transmit rates to absorb bursty traffic.

摘要翻译： 本发明提供一种向活动队列管理算法应用“迟滞”的计算机网络方法和系统。 如果队列处于低于某个低阈值的水平，并且一​​群数据包到达网络节点，则重新计算突发中丢弃初始数据包的概率，但不会丢弃数据包。 然而，如果队列级别超过滞后阈值，则根据丢弃概率丢弃数据包。 此外，根据本发明，可以减少队列级别，直到其变得小于滞后阈值，其中每个丢弃概率的分组丢弃，直到队列级别降低到至少低阈值。 在一个实施例中，还提供自适应算法来调整每个流的发送概率以及迟滞以增加分组传输速率以吸收突发业务。