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公开(公告)号：US07577151B2
公开(公告)日：2009-08-18
申请号：US11096571
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L45/745 , H04L45/00 , H04L45/54
摘要： Method and apparatus for implementing use of a network connection table. In one aspect, searching for network connections includes receiving a packet, and zeroing particular fields of connection information from the packet if a new connection is to be established. The connection information is converted to an address for a location in a direct table using a table access process. The direct table stores patterns and reference information for new and existing connections. The connection information is compared with at least one pattern stored in the direct table at the address to find reference information for the received packet.
摘要翻译： 实现网络连接表使用的方法和装置。 在一个方面，搜索网络连接包括接收分组，并且如果要建立新的连接，则从分组归零特定的连接信息字段。 使用表访问进程将连接信息转换为直接表中的位置的地址。 直接表存储新连接和现有连接的模式和参考信息。 将连接信息与存储在地址中的直接表中的至少一个模式进行比较，以找到所接收的分组的参考信息。
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公开(公告)号：US07881332B2
公开(公告)日：2011-02-01
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译： 根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。 这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。 高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。 最后，该系统允许适配器为多个数据源使用相同的引脚。
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23.发明授权Method for scheduling, writing, and reading data inside the partitioned buffer of a switch, router or packet processing device 失效在交换机，路由器或分组处理设备的分区缓冲区内调度，写入和读取数据的方法公开(公告)号：US07903687B2
公开(公告)日：2011-03-08
申请号：US11096363
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
CPC分类号： H04L49/901 , H04J3/0632 , H04L47/50 , H04L49/90 , H04L49/9031
摘要： A method for receiving packets in a computer network are disclosed. The method include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.
摘要翻译： 公开了一种在计算机网络中接收分组的方法。 该方法包括提供至少一个接收端口，缓冲器，调度器和包装端口。 缓冲器具有与至少一个接收端口和输出端耦合的输入。 调度器具有耦合到缓冲器的输出的第一输入，耦合到包装端口的第二输入和输出。
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公开(公告)号：US07782888B2
公开(公告)日：2010-08-24
申请号：US11953820
申请日：2007-12-10
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译： 根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。 这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。 高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。 最后，该系统允许适配器为多个数据源使用相同的引脚。
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公开(公告)号：US07697536B2
公开(公告)日：2010-04-13
申请号：US11097051
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg , Kyle A. Lucke , Harvey G. Kiel
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg , Kyle A. Lucke , Harvey G. Kiel
IPC分类号： H04L12/56
摘要： Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.
摘要翻译： 提供操作系统分区与计算机网络之间的通信。 一方面，一种用于在多个操作系统分区之间分配网络通信的装置包括允许网络和计算机系统之间的通信的物理端口以及与物理端口相关联的逻辑端口，其中每个逻辑端口与操作系统之一相关联 分区。 每个逻辑端口实现物理端口与相关联的操作系统分区之间的通信，并允许系统的网络资源的可配置性。 其他方面包括用于逻辑和物理端口的逻辑交换机，以及每个连接和每个逻辑端口的分组队列。
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26.发明授权Method for defining and controlling the overall behavior of a network processor device 有权用于定义和控制网络处理器设备的整体行为的方法公开(公告)号：US06763375B1
公开(公告)日：2004-07-13
申请号：US09547362
申请日：2000-04-11
申请人： Claude Basso , Anthony Matteo Gallo , Marco C. Heddes , Seeta Hariharan , Sridhar Rao , Sonia Kiang Rovner
发明人： Claude Basso , Anthony Matteo Gallo , Marco C. Heddes , Seeta Hariharan , Sridhar Rao , Sonia Kiang Rovner
IPC分类号： G06F1300
CPC分类号： H04L41/0803 , H04L29/06 , H04L69/18
摘要： A system and method for controlling overall behavior of a network processor device implemented in a network processing environment servicing a communications network. The method includes steps of receiving a guided control frame including one or more control functions for configuring various functional devices within the network processor with device control parameter data; a step of forwarding one or more control functions from a received control frame to a functional device within the network processor to be configured; and, executing the control functions as specified in the control frame. A novel control frame data structure and communications infrastructure is implemented whereby any network processor device operating in a distributed network processing environment may be controlled in accordance with executed control functions and device control parameter data.
摘要翻译： 一种用于控制在为通信网络服务的网络处理环境中实现的网络处理器设备的整体行为的系统和方法。 该方法包括以下步骤：接收包括用于使用设备控制参数数据配置网络处理器内的各种功能设备的一个或多个控制功能的引导控制帧; 将一个或多个控制功能从接收到的控制帧转发到要配置的网络处理器内的功能设备的步骤; 并且执行控制帧中指定的控制功能。 实现新颖的控制帧数据结构和通信基础设施，从而可以根据执行的控制功能和设备控制参数数据来控制在分布式网络处理环境中操作的任何网络处理器设备。
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公开(公告)号：US08037439B2
公开(公告)日：2011-10-11
申请号：US12126953
申请日：2008-05-26
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译： 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。
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公开(公告)号：US20080229271A1
公开(公告)日：2008-09-18
申请号：US12126951
申请日：2008-05-26
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译： 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。
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公开(公告)号：US07395517B2
公开(公告)日：2008-07-01
申请号：US11230956
申请日：2005-09-20
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译： 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。
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公开(公告)号：US07376809B2
公开(公告)日：2008-05-20
申请号：US11076218
申请日：2005-03-09
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。
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