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公开(公告)号:US07921396B2
公开(公告)日:2011-04-05
申请号:US12126951
申请日:2008-05-26
IPC分类号: G06F17/50
CPC分类号: H04L69/16 , H04L49/45 , H04L69/161
摘要: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
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公开(公告)号:US08037439B2
公开(公告)日:2011-10-11
申请号:US12126953
申请日:2008-05-26
IPC分类号: G06F17/50
CPC分类号: H04L69/16 , H04L49/45 , H04L69/161
摘要: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译: 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列(FPGA)中的硬件宏来最小化移动数据字节所需的可配置逻辑块(CLB)的数量。 与专用集成电路相比,对准机制允许灵活性,可扩展性,可配置性和降低的成本。
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公开(公告)号:US20080229271A1
公开(公告)日:2008-09-18
申请号:US12126951
申请日:2008-05-26
CPC分类号: H04L69/16 , H04L49/45 , H04L69/161
摘要: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译: 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列(FPGA)中的硬件宏来最小化移动数据字节所需的可配置逻辑块(CLB)的数量。 与专用集成电路相比,对准机制允许灵活性,可扩展性,可配置性和降低的成本。
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公开(公告)号:US07395517B2
公开(公告)日:2008-07-01
申请号:US11230956
申请日:2005-09-20
IPC分类号: G06F17/50
CPC分类号: H04L69/16 , H04L49/45 , H04L69/161
摘要: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译: 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列(FPGA)中的硬件宏来最小化移动数据字节所需的可配置逻辑块(CLB)的数量。 与专用集成电路相比,对准机制允许灵活性,可扩展性,可配置性和降低的成本。
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公开(公告)号:US20080229272A1
公开(公告)日:2008-09-18
申请号:US12126953
申请日:2008-05-26
CPC分类号: H04L69/16 , H04L49/45 , H04L69/161
摘要: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
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公开(公告)号:US07904617B2
公开(公告)日:2011-03-08
申请号:US12100739
申请日:2008-04-10
申请人: Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人: Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
CPC分类号: H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块,每个数据缓冲器一个,每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征,其是可设置为“一”或“零”的单个位,并且指示何时发送具有最后位的数据缓冲器。 当附加数据缓冲器被链接到先前的数据缓冲器,指示要发送附加数据缓冲器时,最后一位处于第一位置,而当没有附加数据缓冲器被链接到先前数据缓冲器时,最后一位处于第一位置。 最后一位的位置被传送到指示特定帧的结束的网络处理器。
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公开(公告)号:US07627701B2
公开(公告)日:2009-12-01
申请号:US12120419
申请日:2008-05-14
申请人: Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人: Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
CPC分类号: H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块,每个数据缓冲器一个,每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征,其是可设置为“一个或”零“的单个位,并且指示何时数据缓冲器具有最后位,当最后一位处于第一位置时,当附加数据缓冲器为 被链接到先前的数据缓冲器,指示要发送附加数据缓冲器,并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置,最后位的位置被传送到指示结束的网络处理器 的特定框架。
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公开(公告)号:US07577151B2
公开(公告)日:2009-08-18
申请号:US11096571
申请日:2005-04-01
申请人: Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人: Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号: H04L12/56
CPC分类号: H04L45/745 , H04L45/00 , H04L45/54
摘要: Method and apparatus for implementing use of a network connection table. In one aspect, searching for network connections includes receiving a packet, and zeroing particular fields of connection information from the packet if a new connection is to be established. The connection information is converted to an address for a location in a direct table using a table access process. The direct table stores patterns and reference information for new and existing connections. The connection information is compared with at least one pattern stored in the direct table at the address to find reference information for the received packet.
摘要翻译: 实现网络连接表使用的方法和装置。 在一个方面,搜索网络连接包括接收分组,并且如果要建立新的连接,则从分组归零特定的连接信息字段。 使用表访问进程将连接信息转换为直接表中的位置的地址。 直接表存储新连接和现有连接的模式和参考信息。 将连接信息与存储在地址中的直接表中的至少一个模式进行比较,以找到所接收的分组的参考信息。
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公开(公告)号:US07474662B2
公开(公告)日:2009-01-06
申请号:US11119329
申请日:2005-04-29
申请人: Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人: Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号: H04L12/56
CPC分类号: H04L47/623 , H04L47/50 , H04L47/568
摘要: Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
摘要翻译: 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器,其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中,四入口日历结构提供速率受限加权最佳努力调度。 多个不同流中的每一个都具有相关联的调度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块都有一个计数器,并根据相应数据包所属的流的带宽优先级分配速率限制。 每当从存储链表的最先进先出缓冲器访问调度控制块时,调度器生成调度事件,并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其速率限制时,调度控制块暂时从进一步调度中移除,直到时间间隔结束。
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公开(公告)号:US07409520B2
公开(公告)日:2008-08-05
申请号:US11042692
申请日:2005-01-25
申请人: Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人: Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号: G06F12/00
CPC分类号: G06F9/3851 , G06F9/3802 , G06F9/4843
摘要: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译: 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地,公开了硬件和软件,用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行,则选择补充线程执行。
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