公开(公告)号：US07222318B2

公开(公告)日：2007-05-22

申请号：US10627933

申请日：2003-07-25

申请人： Adi Srinivasan

发明人： Adi Srinivasan

IPC分类号： G06F17/05

CPC分类号： G06F17/505

摘要： A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.

摘要翻译： 提供了一种用于优化延迟插入以减少定时违规的方法。 该方法包括在定时路径中的驱动器和接收器之间插入缓冲器，并将缓冲器放置在包围驱动器和接收器的边界盒的内部或外部。 缓冲区在边界框内或外部的位置在缓冲区上产生适当的有效载荷，以产生所需的最小延迟以避免定时违规。

公开(公告)号：US5319261A

公开(公告)日：1994-06-07

申请号：US922337

申请日：1992-07-30

申请人： Adi Srinivasan ,  Hong Cai ,  Ta-Pen Guo

发明人： Adi Srinivasan ,  Hong Cai ,  Ta-Pen Guo

IPC分类号： H03K17/00 ,  H03K17/693 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094

CPC分类号： H03K19/1776 ,  H03K17/693 ,  H03K19/17704 ,  H03K19/17736

摘要： A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M

摘要翻译： 提供了第一用户可重新编程的互连架构，其中N个开关元件连接在选定的互连导体之间。 开关元件由M个主动存储元件控制，其中M

公开(公告)号：US5257239A

公开(公告)日：1993-10-26

申请号：US913692

申请日：1992-07-14

申请人： Ta-Pen Guo ,  Adi Srinivasan

发明人： Ta-Pen Guo ,  Adi Srinivasan

IPC分类号： G11C11/41 ,  G11C7/20 ,  G11C11/401 ,  G11C11/40

CPC分类号： G11C7/20

摘要： Apparatus for forcing a memory cell to a known state upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and the bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.CC reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V.sub.CC, thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V.sub.CC final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and the bit lines and V.sub.CC.

公开(公告)号：US20080141192A1

公开(公告)日：2008-06-12

申请号：US12016467

申请日：2008-01-18

申请人： RAJIT CHANDRA ,  Adi Srinivasan

发明人： RAJIT CHANDRA ,  Adi Srinivasan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5009 ,  G06F2217/78 ,  G06F2217/80

摘要： A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.

摘要翻译： 公开了一种使用半导体芯片设计的全芯片热分析来计算热导率的方法和装置。 用于分析包括多个物理层的半导体芯片设计的导电性的新方法的一个实施例包括限定多个物理层内的至少一个热层，其中热层代表热导率的变化相对 到半导体芯片设计的其余部分，并计算热层的热导率。 由于热层表示半导体芯片设计上的热导率的变化，热层不一定对应于半导体芯片设计的物理层一一对应。 因此，可以从热层计算半导体芯片设计中的热导率。

公开(公告)号：US07003741B2

公开(公告)日：2006-02-21

申请号：US10838811

申请日：2004-05-03

申请人： Adi Srinivasan

发明人： Adi Srinivasan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an optimal driver for driving the predetermined capacitive load which. simultaneously minimizes the delay and the amount of input capacitance introduced. In one embodiment, a method for selecting a driver for driving a load capacitance from a group of drivers includes: computing for each driver a cost based on a cost function associated with the driver, and selecting the driver having the smallest cost. The cost function is directly proportional to a delay of the driver and inversely proportional to the logarithm of a stage gain of the driver. In another embodiment, the stage gain is an output capacitance driven by the driver (the load capacitance) divided by an input capacitance of the driver.

摘要翻译： 用于最佳驾驶员选择的方法使用基于非线性延迟特性和候选驾驶员的阶段增益的成本函数。 成本函数用于选择用于驱动预定电容负载的最佳驱动器。 同时最小化引入的输入电容的延迟和量。 在一个实施例中，一种用于从一组驱动器中选择用于驱动负载电容的驱动器的方法包括：基于与驱动器相关联的成本函数计算每个驱动器的成本，并选择具有最小成本的驱动器。 成本函数与驱动器的延迟成正比，与驱动器的级增益的对数成反比。 在另一个实施例中，级增益是由驱动器（负载电容）驱动的输出电容除以驱动器的输入电容。

公开(公告)号：US06754877B1

公开(公告)日：2004-06-22

申请号：US10022747

申请日：2001-12-14

申请人： Adi Srinivasan

发明人： Adi Srinivasan

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for optimal driver selection uses a cost function that is based on the non-linear delay characteristics and the stage gain of the candidate drivers. The cost function operates to select an optimal driver for driving the predetermined capacitive load which simultaneously minimizes the delay and the amount of input capacitance introduced. In one embodiment, a method for selecting a driver for driving a load capacitance from a group of drivers includes: computing for each driver a cost based on a cost function associated with the driver, and selecting the driver having the smallest cost. The cost function is directly proportional to a delay of the driver and inversely proportional to the logarithm of a stage gain of the driver. In another embodiment, the stage gain is an output capacitance driven by the driver (the load capacitance) divided by an input capacitance of the driver.

摘要翻译： 用于最佳驾驶员选择的方法使用基于非线性延迟特性和候选驾驶员的阶段增益的成本函数。 成本函数用于选择用于驱动预定电容负载的最佳驱动器，其同时使延迟和引入的输入电容的量最小化。 在一个实施例中，一种用于从一组驱动器中选择用于驱动负载电容的驱动器的方法包括：基于与驱动器相关联的成本函数计算每个驱动器的成本，并选择具有最小成本的驱动器。 成本函数与驱动器的延迟成正比，与驱动器的级增益的对数成反比。 在另一个实施例中，级增益是由驱动器（负载电容）驱动的输出电容除以驱动器的输入电容。

公开(公告)号：US06701506B1

公开(公告)日：2004-03-02

申请号：US10022743

申请日：2001-12-14

申请人： Adi Srinivasan ,  David L. Allen

发明人： Adi Srinivasan ,  David L. Allen

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F1/10 ,  H03K5/1506

摘要： A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserting a delay in a node in an electrical design associated with a logic gate includes: adding the delay at the node by adding a new logic gate before the node where the new logic gate is the same cell type as the logic gate and is positioned near the logic gate. The method may further include: determining if the delay can be added by adding a new logic gate before the node, and if a new logic gate cannot be added before the node, adding the delay by adding a new logic gate after the logic gate where a combination of the logic gate and the new logic gate giving the delay to be added.

摘要翻译： 提供了一种“匹配延迟”缓冲器插入的方法，用于在节点处增加延迟，而不会改变节点的输入电容，如上游节点所见。 在一个实施例中，一种用于在与逻辑门相关联的电气设计中的节点中插入延迟的方法包括：通过在新逻辑门与新逻辑门相同的单元类型的节点之前添加新的逻辑门来在节点添加延迟， 逻辑门并位于逻辑门附近。 该方法还可以包括：通过在节点之前添加新的逻辑门来确定延迟是否可以被添加，并且如果在节点之前不能添加新的逻辑门，则通过在逻辑门之后添加新的逻辑门来添加延迟， 逻辑门和新逻辑门的组合给出了要添加的延迟。

公开(公告)号：US5400294A

公开(公告)日：1995-03-21

申请号：US162585

申请日：1993-12-06

申请人： Adi Srinivasan ,  Ta-Pen Guo

发明人： Adi Srinivasan ,  Ta-Pen Guo

IPC分类号： G11C7/20 ,  G11C7/22 ,  G11C11/40

CPC分类号： G11C7/20 ,  G11C7/22

摘要： Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.CC reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V.sub.CC, thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V.sub.CC final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and the bit lines and V.sub.CC.

摘要翻译： 用于在上电时将存储器单元强制为用户选择的逻辑电平的装置包括用于提供在芯片上电期间使用的两个信号PWRUP和PWRUPB的电路。 上电时，当VCC从0伏升至3.5伏时，PWRUP信号遵循VCC，PWRUPB信号保持0伏。 PWRUP和PWRUPB信号分别用于驱动P沟道和N沟道MOS晶体管的栅极，包括连接在字线驱动电路和驱动与存储单元相关联的字线和位线驱动电路之间的通路 。 此外，PWRUPB信号用于驱动连接在字线与VCC和位线和VCC之间的P沟道MOS上拉晶体管。 在上电期间，禁止通过门，将字线和位线与驱动器断开。 字线和位线被迫通过P沟道上拉晶体管跟随VCC的上升。 当VCC达到所需值时，PWRUP信号变为0伏，PWRUPB信号变为VCC，从而打开通过门，将字线和位线驱动电路连接到字线和位线。 VCC最终PWRUPB信号关闭连接在字线和VCC与位线和VCC之间的P沟道MOS上拉晶体管。

公开(公告)号：US5315545A

公开(公告)日：1994-05-24

申请号：US77299

申请日：1993-06-15

申请人： Ta-Pan Guo ,  Adi Srinivasan

发明人： Ta-Pan Guo ,  Adi Srinivasan

IPC分类号： G11C11/412 ,  G11C11/419 ,  H03K3/356 ,  G11C11/40

CPC分类号： H03K3/356156 ,  G11C11/412 ,  G11C11/419

摘要： According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V.sub.SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V.sub.HS, and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V.sub.SS. The gates of the first and second P-Channel MOS transistors are cross-coupled and the gates of the second and fourth N-Channel MOS transistors are cross-coupled. The gates of the first and third N-Channel MOS transistors are connected together to power supply rail V.sub.DD, usually 5 volts. The first and second P-Channel MOS transistors are formed in an n-well biased at a constant power supply voltage. In a preferred embodiment the constant power supply voltage may be V.sub.HS. A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.

摘要翻译： 根据本发明的第一方面，根据本发明的静态随机存取存储单元包括两个阶段。 第一级具有第一P沟道MOS晶体管，其源极连接到高压电源轨，其漏极连接到第一N沟道MOS晶体管的漏极。 第一N沟道MOS晶体管的源极连接到第二N沟道MOS晶体管的漏极。 第二N沟道MOS晶体管的源极连接到VSS电源轨。 第二级具有第二P沟道MOS晶体管，其源极连接到高压电源轨VHS，其漏极连接到第三N沟道MOS晶体管的漏极。 第三N沟道MOS晶体管的源极连接到第四N沟道MOS晶体管的漏极。 第四个N沟道MOS晶体管的源极连接到VSS。 第一和第二P沟道MOS晶体管的栅极交叉耦合，并且第二和第四N沟道MOS晶体管的栅极交叉耦合。 第一和第三N沟道MOS晶体管的栅极连接到电源轨VDD，通常为5伏。 第一和第二P沟道MOS晶体管形成为以恒定电源电压的n-阱偏置。 在优选实施例中，恒定电源电压可以是VHS。 通过第五N沟道MOS晶体管耦合到第二N沟道MOS晶体管的漏极的位线，其栅极连接到字线。