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21.发明授权公开(公告)号：US06735690B1
公开(公告)日：2004-05-11
申请号：US09598566
申请日：2000-06-21
IPC分类号： G06F1500
CPC分类号： G06F9/30054 , G06F9/30101 , G06F9/30112 , G06F9/325
摘要： A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur. The generalized facilities are defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters, namely at least one register to compare against, a register containing a second compare register, a vector address, or parameter to be passed, and a count or mask register. Based upon this generalized eventpoint architecture, new capabilities are enabled. For example, auto-looping with capabilities to branch out of a nested auto-loop upon detection of a specified condition, background DMA facilities, the ability to link a chain of p-events together for debug purposes, and others are all important capabilities which are readily obtained.
摘要翻译： 描述了具有广泛事件点架构的处理器，其可扩展以用于非常长的指令字（VLIW）阵列处理器，例如歧管阵列（ManArray）处理器。 在一个方面，通过使用比较来提供广义处理器事件（p事件）检测设施，以检查指令地址，数据存储器地址，指令，数据值，算术条件标志或其他处理器状态变化 事件点已发生。 在另一方面，提供通用处理器动作（p-action）功能以通过用新的指令地址加载程序计数器来产生程序流程的改变，生成中断，信号信号，记录或计数p事件， 事件时间戳，启动后台操作，或导致其他动作发生。 广义设施在事件点架构中被定义为由控制寄存器和三个事件点参数组成，即至少要有一个要比较的寄存器，一个包含第二个比较寄存器的寄存器，一个向量地址或要传递的参数，以及一个计数 或屏蔽寄存器。 基于这种广义的事件点架构，启用了新的功能。 例如，在检测到指定的条件时，自动循环具有分支出嵌套自动循环的功能，后台DMA设施，将p个事件链链接在一起用于调试目的的能力等等都是重要的功能 容易获得。
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22.发明授权Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision 有权动态指令控制重配置寄存器文件的扩展精度的方法和装置公开(公告)号：US06343356B1
公开(公告)日：2002-01-29
申请号：US09169255
申请日：1998-10-09
申请人： Gerald G. Pechanek , Edwin F. Barry
发明人： Gerald G. Pechanek , Edwin F. Barry
IPC分类号： G06F930
CPC分类号： G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016
摘要： A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
摘要翻译： 描述集成在能够进行扩展精度操作并且还能够对较低精度数据进行并行操作的指令集架构中的可重配置寄存器文件。 注册文件由两个单独的文件组成，每个文件的每个文件包含与原始文件一样多的寄存器。 这两半由于它们包含的寄存器地址而被指定为偶数或奇数。 单个宽度和双宽度操作数得到最佳支持，而不增加寄存器文件大小，而不增加寄存器文件端口数量。 还使用单独的扩展寄存器来为诸如乘法累加操作的操作提供扩展精度。
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23.发明授权
公开(公告)号：US06101592A
公开(公告)日：2000-08-08
申请号：US215081
申请日：1998-12-18
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
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公开(公告)号：US07010668B2
公开(公告)日：2006-03-07
申请号：US10650340
申请日：2003-08-28
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
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25.发明授权Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode 失效控制处理器在灵活耦合模式下动态加载与协处理器的内存条目相关联的影子指令寄存器公开(公告)号：US06865663B2
公开(公告)日：2005-03-08
申请号：US09792819
申请日：2001-02-23
申请人： Edwin F. Barry
发明人： Edwin F. Barry
CPC分类号： G06F9/3885 , G06F9/321 , G06F9/327 , G06F9/3814 , G06F9/3881 , G06F11/3656
摘要： A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.
摘要翻译： 描述了在协处理器和控制处理器之间提供灵活耦合的方法和系统。 该系统包括协处理器和连接协处理器与控制处理器的系统控制总线。 协处理器有两种访问模式。 在第一访问模式中，协处理器检索存储在指令存储器中的指令，并且在第二访问模式中，协处理器从控制处理器检索指令。 系统控制总线提供了一个将指令加载到协处理器的阴影指令寄存器的路径。 协处理器在检索与阴影指令接收器相关联的指令存储器中的条目时，确定是将该指令加载到程序计数器中的地址还是将影子指令寄存器的内容加载到指令解码寄存器中。
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26.发明授权Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision 失效用于动态指令控制可重配置寄存器文件的方法和装置，具有更高的精度公开(公告)号：US06430677B2
公开(公告)日：2002-08-06
申请号：US09796037
申请日：2001-02-28
申请人： Gerald G. Pechanek , Edwin F. Barry
发明人： Gerald G. Pechanek , Edwin F. Barry
IPC分类号： G06F1500
CPC分类号： G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016
摘要： A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
摘要翻译： 描述集成在能够进行扩展精度操作并且还能够对较低精度数据进行并行操作的指令集架构中的可重配置寄存器文件。 注册文件由两个单独的文件组成，每个文件的每个文件包含与原始文件一样多的寄存器。 这两半由于它们包含的寄存器地址而被指定为偶数或奇数。 单个宽度和双宽度操作数得到最佳支持，而不增加寄存器文件大小，而不增加寄存器文件端口数量。 还使用单独的扩展寄存器来为诸如乘法累加操作的操作提供扩展精度。
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27.发明授权Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置公开(公告)号：US06366999B1
公开(公告)日：2002-04-02
申请号：US09238446
申请日：1999-01-28
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译： 使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。 每个添加的位提供了先前功能的超集。 通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。 通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。 多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。 多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。
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28.发明授权Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置公开(公告)号：US06775766B2
公开(公告)日：2004-08-10
申请号：US09796040
申请日：2001-02-28
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。 通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。 通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。 当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。 因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。 此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。 这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。
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29.发明授权公开(公告)号：US06557094B2
公开(公告)日：2003-04-29
申请号：US09969077
申请日：2001-09-28
IPC分类号： G06F1580
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
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30.发明授权Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor 有权用于动态超长指令字子指令选择的方法和装置，用于间接非常长的指令字处理器中的执行时间并行性公开(公告)号：US06467036B1
公开(公告)日：2002-10-15
申请号：US09717992
申请日：2000-11-21
IPC分类号： G06F1580
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3822 , G06F9/3853
摘要： A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit's VIM can be independently addressed thereby removing duplicate SIWs within the functional unit's VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.
摘要翻译： 流水线数据处理单元包括指令定序器和能够并行执行n个操作的n个功能单元。 指令定序器包括用于存储在涉及并行执行两个或多个功能单元的操作中使用的非常长的指令字（VLIW）的随机存取存储器。 每个VLIW包括多个短指令字（SIW），其中每个SIW对应于与唯一功能单元相关联的唯一类型的指令。 VLIW通过在每个地址或条目中加载和连接SIW来组成VLIW存储器。 VLIW通过执行VLIW（XV）指令执行。 通过使用XV1指令中包含的掩码字段，可以在VLIW存储器地址处压缩iVLIW，该掩码字段指定在执行VLIW期间启用或禁用哪些功能单元。 每次执行XV1指令时，可以更改掩码，每次执行时都可以有效地修改VLIW。 VLIW存储器（VIM）可以被进一步划分成各自与功能解码和执行单元相关联的存储器。 通过第二执行VLIW指令XV2，可以独立地对每个功能单元的VIM进行寻址，从而去除功能单元的VIM内的重复SIW。 这提供了VLIW存储器的进一步优化，从而允许在成本敏感的应用中使用较小的VLIW存储器。
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