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    ELECTRODE SELECTION DEVICE FOR SELECTING OPTIMAL ELECTRODES TO COMMUNICATE WITH CAPSULE ENDOSCOPE, AND OPERATION METHOD THEREOF
    22.
    发明申请
    ELECTRODE SELECTION DEVICE FOR SELECTING OPTIMAL ELECTRODES TO COMMUNICATE WITH CAPSULE ENDOSCOPE, AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190335984A1

    公开(公告)日：2019-11-07

    申请号：US16402164

    申请日：2019-05-02

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Mi Jeong PARK ,  Hyung-IL PARK ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Kwang IL OH ,  Jae-Jin LEE ,  In Gi LIM

    IPC: A61B1/04 ,  H04B13/00 ,  A61B1/00

    Abstract: Provided is and electrode selection device communicating with a capsule endoscope. The device includes an analog front end configured to recover first data based on first signals transmitted from the capsule endoscope to a first electrode and a second electrode, recover second data based on second signals transmitted from the capsule endoscope to the first electrode and a third electrode, and recover third data based on third signals transmitted from the capsule endoscope to the second electrode and the third electrode, and a digital receiver configured to calculate a first correlation value between the first and second electrodes, a second correlation value between the first and third electrodes, and a third correlation value between the second and third electrodes based on the first to third data. The digital receiver calculates, among the first to third correlation values, a first correlation sum obtained by adding first and second correlation values generated using the first electrode, a second correlation sum obtained by adding the first and third correlation values generated using the second electrode, and a third correlation sum obtained by adding the second and third correlation values generated using the third electrode, and selects a receiving electrode pair among the first to third electrodes based on the first to third correlation sums.

    LDPC ENCODER AND LDPC ENCODING METHOD
    23.
    发明申请
    LDPC ENCODER AND LDPC ENCODING METHOD 审中-公开

    公开(公告)号：US20190238157A1

    公开(公告)日：2019-08-01

    申请号：US16166789

    申请日：2018-10-22

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Hyuk KIM ,  In-San JEON

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/116 ,  H03M13/611 ,  H03M13/616 ,  H03M13/618

    Abstract: An LDPC encoding method of a computing device is provided. The computing device performs LDCP encoding on information with a parity check matrix with R rows and (C+R) columns defining an LDPC code. When the parity check matrix is divided into a first matrix with R rows and R columns and a second matrix with R rows and R columns, each element of the first matrix indicates a number of times an identity matrix with Z rows and Z columns are circularly shifted. All elements in the first row of the first matrix are 0. In the r-th row of the first matrix, elements obtained by performing a modulo Z operation (mod Z) on values which are sequentially incremented by (r−1) starting from 0 are arranged. R, C, and Z are natural numbers, and r is an integer from 2 to R.

    LOW DENSITY PARITY CHECK DECODER USING BINARY LOGARITHM AND DECODING METHOD THEREOF
    24.
    发明申请
    LOW DENSITY PARITY CHECK DECODER USING BINARY LOGARITHM AND DECODING METHOD THEREOF 审中-公开

    公开(公告)号：US20180358983A1

    公开(公告)日：2018-12-13

    申请号：US15803073

    申请日：2017-11-03

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Hyuk KIM ,  Insan JEON

    IPC: H03M13/11

    CPC classification number: H03M13/1125 ,  G06F17/13 ,  H03M13/1108 ,  H03M13/1134 ,  H03M13/114

    Abstract: Provided is a low density parity check (LDPC) decoder. An LDPC decoder according to an embodiment of the inventive concept includes a variable node calculator for adding an input log-likelihood ratio (LLR) to message information of a check node to output the added values, a check node calculator for extracting signs of the output values of the variable node calculator, determining a minimum value of the output values, and calculating a correction term for the output values by using a binary logarithm to transmit to the variable node calculator, a hard decision block for determining bit values of the output values of the variable node calculator, and a parity check block for performing a parity check operation for determining validity of the bit value.

    SPIKING NEURAL NETWORK CIRCUITS GENERATING SPIKE SIGNALS AND METHOD OF OPERATION THEREOF
    25.
    发明申请
    SPIKING NEURAL NETWORK CIRCUITS GENERATING SPIKE SIGNALS AND METHOD OF OPERATION THEREOF 有权

    公开(公告)号：US20240428047A1

    公开(公告)日：2024-12-26

    申请号：US18422776

    申请日：2024-01-25

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Hyuk KIM ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates first and second input spike signals, a synapse circuit that generates a first current based on the first input spike signal and a weight and generates a second current based on the second input spike signal and the weight, a capacitor that forms a first membrane voltage based on the first current, and a neuron circuit including a comparator and that resets the first membrane voltage, and after the capacitor further forms a second membrane voltage based on the second current, and the comparator includes a first input terminal and a second input terminal, receives the first membrane voltage through the first input terminal and a reference voltage through the second input terminal, generates a first spike signal based on a first comparison operation of the first membrane voltage and the reference voltage.

    LOW POWER SYSTEM ON CHIP
    29.
    发明申请
    LOW POWER SYSTEM ON CHIP 有权

    公开(公告)号：US20220413544A1

    公开(公告)日：2022-12-29

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung HAN ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Kwang IL OH ,  Jae-Jin LEE

    IPC: G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

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