公开(公告)号：US06380067B1

公开(公告)日：2002-04-30

申请号：US09588119

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

IPC分类号： H01L21302

CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

摘要翻译： 本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。 在一个实施例中，电子器件形成在半导体衬底上。 然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。 然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。 然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。 然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。 光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

公开(公告)号：US06294460B1

公开(公告)日：2001-09-25

申请号：US09586254

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

IPC分类号： H01L214763

CPC分类号： H01L21/7688 ,  H01L21/76802 ,  Y10S438/952

摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.

摘要翻译： 提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。 在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，并且BARC沉积在电介质层的顶部上。 BARC通过PECVD沉积，以使BARC富集半导体材料，以增加BARC的消光系数，从而减小其厚度。 然后将厚度小于BARC的厚度的光致抗蚀剂层沉积在BARC的顶部。 然后将光致抗蚀剂图案化，光刻加工，显影和除去。 然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。 然后将BARC用作蚀刻电介质层的掩模。 导电材料沉积在BARC和电介质层上，随后在抛光导电材料的过程中被去除，而不需要单独的BARC去除步骤。

公开(公告)号：US5998301A

公开(公告)日：1999-12-07

申请号：US993252

申请日：1997-12-18

申请人： Tuan D. Pham ,  Angela T. Hui ,  Kashmir Sahota

发明人： Tuan D. Pham ,  Angela T. Hui ,  Kashmir Sahota

IPC分类号： H01L21/8247 ,  H01L21/76 ,  H01L21/762 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/308

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.

摘要翻译： 公开了一种用于在半导体上提供浅沟槽隔离结构轮廓的方法和系统。 该方法和系统包括在半导体衬底上图案化掩模，蚀刻掩模使得掩模具有倾斜的侧面，蚀刻半导体衬底以形成沟槽，由此沟槽具有锥形侧面，并平坦化半导体衬底以优化沟槽深度， 用于后续处理的沟槽开口的宽度。 根据本文公开的方法和系统，本发明允许形成具有锥形侧面的浅沟槽隔离结构轮廓。