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21.发明授权Method and device for synchronization and identification of the codegroup in cellular communication systems and computer program product therefor 有权用于蜂窝通信系统中的代码组的同步和识别的方法和设备及其计算机程序产品公开(公告)号：US07123929B2
公开(公告)日：2006-10-17
申请号：US10717433
申请日：2003-11-18
申请人： Giuseppe Avellone , Francesco Rimi , Francesco Pappalardo , Agostino Galluzzo , Giuseppe Visalli
发明人： Giuseppe Avellone , Francesco Rimi , Francesco Pappalardo , Agostino Galluzzo , Giuseppe Visalli
CPC分类号： H04B1/70735 , H04B1/7083
摘要： Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation of the received signal (r) with the synchronization codes, the information corresponding to the codegroup and to the fine slot synchronization. The synchronization codes are split into codesets. In a first step, a synchronization code identifying a corresponding codeset (CS) is identified by means of correlation and search for the maximum value of correlation energy. In a second step, the received signal (r) is correlated with the remaining codes belonging to the codeset identified. The information thus obtained, which corresponds to all the synchronization codes comprised in the codeset identified, is used for obtaining frame synchronization and codegroup identification. Preferential application is in mobile communication systems based upon standards, such as UMTS, CDMA2000, IS95 or WBCDMA.
摘要翻译： 一旦在第一步骤中获得了时隙同步，则在第二步骤期间，通过接收到的信号（r）与同步码的相关性，获得与代码组相对应的信息和精细时隙同步。 同步代码被分为代码集。 在第一步骤中，通过相关性和相关能量的最大值搜索识别相应代码集（CS）的同步码。 在第二步骤中，所接收的信号（r）与所识别的代码集的剩余码相关。 由此获得的与所识别的代码集中包含的所有同步码对应的信息用于获得帧同步和码组识别。 优先应用在基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统中。
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22.发明授权Processor architecture with processing clusters providing vector and scalar data processing capability 有权具有处理集群的处理器架构，提供向量和标量数据处理能力公开(公告)号：US08060725B2
公开(公告)日：2011-11-15
申请号：US11768481
申请日：2007-06-26
IPC分类号： G06F15/00
CPC分类号： G06F9/3012 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.
摘要翻译： 用于多媒体应用的处理器架构包括提供矢量数据处理能力的处理器集群。 处理器集群中的处理元件根据单指令多数据（SIMD）功能处理位长度为N的数据和位长度为N / 2，N / 4等的数据。 负载单元根据相同的指令加载到要处理的处理器集群数据中。 集群间数据路径在处理器集群之间交换数据。 集群间数据路径是可扩展的，以激活所选择的处理器集群。 处理器在SIMD，标量和矢量数据上同时运行。
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23.发明授权Process and devices for transmitting digital signals over buses and computer program product therefore 有权因此，通过总线和计算机程序产品传输数字信号的过程和设备公开(公告)号：US07372916B2
公开(公告)日：2008-05-13
申请号：US10670993
申请日：2003-09-25
IPC分类号： H04L27/00
CPC分类号： G06F13/4072 , G06F13/4213
摘要： Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.
摘要翻译： 数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。 基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定 在前一时刻，以便最小化总线上的开关活动。
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公开(公告)号：US20050283587A1
公开(公告)日：2005-12-22
申请号：US11145780
申请日：2005-06-06
CPC分类号： G06F15/8023 , G06F1/3203 , G06F1/3287 , G06F9/3885 , G06F9/3887 , Y02D10/171 , Y02D50/20
摘要： A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.
摘要翻译： 处理器架构包括用于处理输入信号的多个处理元件。 该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。 相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。 该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。
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25.发明授权Method and system for high-speed floating-point operations and related computer program product 有权高速浮点运算方法与系统及相关计算机程序产品公开(公告)号：US07899860B2
公开(公告)日：2011-03-01
申请号：US11190501
申请日：2005-07-26
摘要： A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.
摘要翻译： 一种用于从包括实际加法输入或至少一个较早进位的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。 优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，其产生与执行的整数相加的结果相同数量的前导零的数字。 进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。
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26.发明授权Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法公开(公告)号：US07817763B2
公开(公告)日：2010-10-19
申请号：US11787194
申请日：2007-04-12
IPC分类号： H04L25/38
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。
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27.发明授权Method and device for transmitting data on a single line, in particular for transmitting data on a bus with minimization of the bus switching activity, and corresponding computer product 有权用于在单个线路上传输数据的方法和装置，特别是用于在总线上传输数据，同时最小化总线切换活动，以及对应的计算机产品公开(公告)号：US07586943B2
公开(公告)日：2009-09-08
申请号：US10757772
申请日：2004-01-14
IPC分类号： H04J3/16
CPC分类号： G06F13/4286
摘要： Described herein is a method for transmitting data on a bus with minimization of the bus switching activity, comprising the steps of converting the datum to be transmitted from its own original format to a transmission format that minimizes the switching activity on the bus, said conversion consisting in swapping the position of one or more bits of the datum to be transmitted, the swapping being performable according to a plurality of different variants, each of which is identified by a respective sorting pattern, and selecting, between the various sorting patterns, an optimal sorting pattern that minimizes the bus switching activity upon transmission on the bus of the datum generated using said optimal sorting pattern.
摘要翻译： 这里描述了一种用于在总线切换活动最小化的情况下在总线上发送数据的方法，包括以下步骤：将要发送的数据从其自己的原始格式转换成使总线上的切换活动最小化的传输格式，所述转换包括 在交换要发送的数据的一个或多个比特的位置时，根据多个不同的变体进行交换，每个不同的变体由相应的分类模式标识，并且在各种分类模式之间选择最优 排序模式，其使用所述最佳排序模式生成的基准总线上的传输最小化总线切换活动。
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28.发明申请Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法公开(公告)号：US20080037667A1
公开(公告)日：2008-02-14
申请号：US11787194
申请日：2007-04-12
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。
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29.发明申请Method and system for high-speed floating-point operations and related computer program product 有权高速浮点运算方法与系统及相关计算机程序产品公开(公告)号：US20070027946A1
公开(公告)日：2007-02-01
申请号：US11190501
申请日：2005-07-26
IPC分类号： G06F7/50
摘要： A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.
摘要翻译： 一种用于从包括实际加法输入或至少一个较早进位的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。 优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，其产生与执行的整数相加的结果相同数量的前导零的数字。 进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。
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30.发明授权Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法公开(公告)号：US08817935B2
公开(公告)日：2014-08-26
申请号：US12844460
申请日：2010-07-27
IPC分类号： H04L25/38
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。
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