公开(公告)号：US5821558A

公开(公告)日：1998-10-13

申请号：US792791

申请日：1997-02-03

Applicant: Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

Inventor： Yu-Pin Han ,  Ying-Tsong Loh ,  Ivan Sanchez

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/04 ,  H01L27/02

CPC classification number: H01L27/11206 ,  H01L27/112

Abstract: An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Abstract translation: 反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。 通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被 在非编程状态下较不易于断态泄漏。 制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

公开(公告)号：US5793640A

公开(公告)日：1998-08-11

申请号：US773171

申请日：1996-12-26

Applicant: Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: G01R27/26 ,  G01R27/00

CPC classification number: G01R27/2605

Abstract: A computer-aided method and system are provided for obtaining a measurement of the capacitance value of a device under test (DUT). The complex impedance of a device under test (DUT) is measured at two nearby frequencies using an RLC meter. The two complex impedance values are then stored in a computer readable medium. The DUT is modeled by a programmed computer as a four element RLC model circuit including a resistor and inductor in series with a parallel RC circuit having a single capacitor which represents the capacitance of the DUT. Four equations which describe the electrical characteristics of the four element RLC model circuit are stored in a computer readable medium. The four measured values of complex impedance are substituted by the computer into the four stored equations. Values are obtained for the four individual RLC circuit elements by solving the four equations. The four unknown values are obtained by use of an optimization routine and then stored to a computer readable medium. The value capacitor element representing the capacitance of the DUT is then displayed.

Abstract translation: 提供了一种计算机辅助方法和系统，用于获得待测器件（DUT）的电容值的测量。 被测设备（DUT）的复阻抗使用RLC仪在两个附近的频率下测量。 然后将两个复阻抗值存储在计算机可读介质中。 DUT被编程的计算机建模为四元件RLC模型电路，其包括与表示DUT的电容的单个电容器的并联RC电路串联的电阻器和电感器。 描述四元素RLC模型电路的电特性的四个等式被存储在计算机可读介质中。 复阻抗的四个测量值被计算机代入四个存储的方程。 通过求解四个等式获得四个单独的RLC电路元件的值。 通过使用优化例程获得四个未知值，然后将其存储到计算机可读介质中。 然后显示表示DUT的电容的值电容器元件。

公开(公告)号：US5773317A

公开(公告)日：1998-06-30

申请号：US572944

申请日：1995-12-15

Applicant: Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

Inventor： Koucheng Wu ,  Yu-Pin Han ,  Ying-Tsong Loh

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002

Abstract: The use of a test chip having a wide channel MOSFETs of different channel widths and effective gate lengths allows for an experimental determination of the fringe capacitance per unit width. The use of channel widths greater than 100 microns increases the accuracy of the measured capacitance values.

Abstract translation: 使用具有不同沟道宽度和有效栅极长度的宽沟道MOSFET的测试芯片允许对每单位宽度的边缘电容进行实验测定。 使用大于100微米的通道宽度会增加测量电容值的精度。

公开(公告)号：US5770892A

公开(公告)日：1998-06-23

申请号：US460494

申请日：1995-06-02

Applicant: Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

Inventor： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11

CPC classification number: H01L28/20 ,  H01L27/0605 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Abstract translation: CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。 在该多晶硅信号线内制造场效应器件。 场效应器件的沟道通过薄栅极介质与衬底中的有源区域分离，衬底内的有源区域用作场效应器件的控制栅极。 这种器件可用于提供用于CMOS SRAM单元的多晶硅P沟道晶体管。

公开(公告)号：US4679300A

公开(公告)日：1987-07-14

申请号：US785195

申请日：1985-10-07

Applicant: Tsiu C. Chan ,  Yu-Pin Han

Inventor： Tsiu C. Chan ,  Yu-Pin Han

IPC: H01L27/04 ,  H01L21/265 ,  H01L21/266 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10861 ,  H01L27/10829 ,  H01L29/94

Abstract: A method of making a trench capacitor employs an N-type switchable plate formed in a P-type substrate for holding charge at either zero volts or a positive TC voltage and a P-type ground plate that fills in a trench around a memory cell, so that P-type dopant diffuses through a thin oxide insulator to form a channel stop and a pinhold short through the oxide is self-healing by the formation of a reverse-biased P-N diode that cuts off the flow of current through the pinhole.

Abstract translation: 制造沟槽电容器的方法采用形成在P型衬底中的N型可切换板，用于保持零电压或正TC电压的电荷，以及填充存储器单元周围的沟槽的P型接地板， 使得P型掺杂剂通过薄氧化物绝缘体扩散以形成通道阻挡层，并且穿过氧化物的引脚短路通过形成反向偏置PN二极管而自愈，其截止通过针孔的电流流动。