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公开(公告)号：US20170059361A1
公开(公告)日：2017-03-02
申请号：US14842578
申请日：2015-09-01
Applicant: General Electric Company
Inventor： Kaustubh Ravindra Nagarkar , Peter William Lorraine
CPC classification number: G01D5/16 , A61B5/062 , G01R33/0005 , G01R33/0017 , G01R33/0052 , G01R33/0206
Abstract: A system and method for providing a position and orientation sensor package having a reduced size in at least one dimension is disclosed. The position and orientation sensor package includes a dielectric substrate and a first magneto-resistance sensor chip attached to the dielectric substrate, the first magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package also includes a second magneto-resistance sensor chip attached to the dielectric substrate and positioned adjacent the first magneto-resistance sensor chip, the second magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package is constructed such that the at least one magneto-resistance sensor circuit of the first magneto-resistance sensor chip is oriented in a different direction than the at least one magneto-resistance sensor circuit of the second magneto-resistance sensor chip.
Abstract translation: 公开了一种用于在至少一个维度上提供尺寸减小的位置和方向传感器封装的系统和方法。 位置和方向传感器封装包括电介质基片和附着在电介质基底上的第一磁阻传感器芯片，第一磁阻传感器芯片包括至少一个磁阻传感器电路。 位置和方向传感器封装还包括附接到电介质基板并且邻近第一磁阻传感器芯片定位的第二磁阻传感器芯片，第二磁阻传感器芯片包括至少一个磁阻传感器电路。 位置和方向传感器封装被构造成使得第一磁阻传感器芯片的至少一个磁阻传感器电路被定向在与第二磁阻传感器的至少一个磁阻传感器电路不同的方向上 芯片。
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22.发明授权公开(公告)号：US10804115B2
公开(公告)日：2020-10-13
申请号：US15668502
申请日：2017-08-03
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L21/48 , H01L21/56 , H01L21/52 , H01L23/31 , H01L23/28 , H01L23/16 , H01L23/00 , H01L23/538 , H01L23/50
Abstract: An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.
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23.发明授权公开(公告)号：US10607929B2
公开(公告)日：2020-03-31
申请号：US16229049
申请日：2018-12-21
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Kaustubh Ravindra Nagarkar , Arun Virupaksha Gowda , James Wilson Rose
IPC: H01L23/498 , H01L21/48 , H01L23/00 , H05K1/18 , H01L23/538
Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.
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24.发明申请公开(公告)号：US20200066544A1
公开(公告)日：2020-02-27
申请号：US16667018
申请日：2019-10-29
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L21/48 , H01L27/146 , H01L23/00 , H01L27/14 , H01L23/367 , H01L23/31 , H01L23/14 , H01L23/28 , H01L21/52 , H01L21/56
Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
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公开(公告)号：US10541209B2
公开(公告)日：2020-01-21
申请号：US15668553
申请日：2017-08-03
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L21/48 , H01L21/56 , H01L21/52 , H01L23/28 , H01L23/552
Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.
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Patent Agency Ranking
公开(公告)号：US10276523B1
公开(公告)日：2019-04-30
申请号：US15816312
申请日：2017-11-17
Applicant: General Electric Company
Inventor： Raymond Albert Fillion , Kaustubh Ravindra Nagarkar
Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.
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27.发明申请公开(公告)号：US20190043810A1
公开(公告)日：2019-02-07
申请号：US15668553
申请日：2017-08-03
Applicant: General Electric Company
Inventor： Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
IPC: H01L23/552 , H01L21/52 , H01L21/56 , H01L21/48
Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.
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公开(公告)号：US09995600B2
公开(公告)日：2018-06-12
申请号：US14842578
申请日：2015-09-01
Applicant: General Electric Company
Inventor： Kaustubh Ravindra Nagarkar , Peter William Lorraine
CPC classification number: G01D5/16 , A61B5/062 , G01R33/0005 , G01R33/0017 , G01R33/0052 , G01R33/0206
Abstract: A system and method for providing a position and orientation sensor package having a reduced size in at least one dimension is disclosed. The position and orientation sensor package includes a dielectric substrate and a first magneto-resistance sensor chip attached to the dielectric substrate, the first magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package also includes a second magneto-resistance sensor chip attached to the dielectric substrate and positioned adjacent the first magneto-resistance sensor chip, the second magneto-resistance sensor chip including at least one magneto-resistance sensor circuit. The position and orientation sensor package is constructed such that the at least one magneto-resistance sensor circuit of the first magneto-resistance sensor chip is oriented in a different direction than the at least one magneto-resistance sensor circuit of the second magneto-resistance sensor chip.
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公开(公告)号：US20180062618A1
公开(公告)日：2018-03-01
申请号：US15246671
申请日：2016-08-25
Applicant: General Electric Company
Inventor： Kaustubh Ravindra Nagarkar , Yongjae Lee , Christopher James Kapusta
CPC classification number: H03H9/54 , H01L2224/18 , H03H3/02 , H03H9/0547 , H03H9/1042 , H03H9/1071 , H03H9/1085 , H03H9/64
Abstract: A filter package and method of manufacturing thereof is disclosed. The filter device package includes a first dielectric layer having an acoustic wave filter device attached thereto, the acoustic wave filter device comprising an active area and I/O pads. The filter device package also includes an adhesive positioned between the first dielectric layer and the acoustic wave filter device to secure the layer to the device, vias formed through the first dielectric layer and the adhesive to the I/O pads of the acoustic wave filter device, and metal interconnects formed in the vias and mechanically and electrically coupled to the I/O pads of the acoustic wave filter device to form electrical interconnections thereto, wherein an air cavity is formed in the adhesive between the acoustic wave filter device and the first dielectric layer, in a location adjacent the active area of the acoustic wave filter device.
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30.发明授权公开(公告)号：US09534855B2
公开(公告)日：2017-01-03
申请号：US14549268
申请日：2014-11-20
Applicant: General Electric Company
Inventor： Shakti Singh Chauhan , Kaustubh Ravindra Nagarkar , Matthew Jeremiah Misner , Faisal Razi Ahmad
CPC classification number: F28F21/02 , B22F1/0018 , B22F3/11 , B22F3/1115 , B22F3/1137 , B22F3/114 , B22F3/24 , B22F7/00 , B22F7/02 , B22F2001/0037 , B22F2998/10 , F28F13/003 , F28F21/00 , F28F21/067 , F28F2255/18 , H01L23/3733 , Y10T428/249955 , Y10T428/249958 , Y10T428/249978 , B22F3/10 , B22F2003/244 , B22F3/26 , B22F2007/045
Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.
Abstract translation: 提供了复合泡沫，其包括设置在这种金属模板上的金属模板和保形原子级膜以形成3维互连结构。 金属模板包括具有多个第一非球形孔，多个第一非球形孔隙和第一表面积与体积比的多个烧结互连。 保形原子级膜具有多个第二非球形孔，第二非球形孔隙率和大约等于第一表面积体积比的第二表面积体积比。 多个烧结互连具有多个树枝状颗粒，并且共形原子尺度膜包括石墨烯层和六方氮化硼层中的至少一个。
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