公开(公告)号：US08339075B2

公开(公告)日：2012-12-25

申请号：US12307152

申请日：2007-07-03

申请人： Gian Hoogzaad

发明人： Gian Hoogzaad

IPC分类号： H02P3/14

CPC分类号： H02P23/20

摘要： Consistent with an example embodiment there is a method for controlling a deceleration process of a DC motor, wherein the DC motor is driven by a bridge driver coupled to a power supply intended to provide a supply voltage VDD at a power supply output. The method comprises applying a deceleration PWM signal to the bridge driver for decelerating the DC motor, and controlling the bridge driver such that a motor-induced back current is reduced, if the voltage at the power supply output exceeds a first voltage threshold which is higher than VDD. In accordance with the example embodiment, the method includes the following: if the voltage at the power supply output falls below a second voltage threshold which is lower than the first voltage threshold, control of the bridge driver is terminated such that the motor-induced back current is reduced.

摘要翻译： 与示例性实施例一致，存在用于控制直流电动机的减速过程的方法，其中直流电动机由耦合到电源的桥式驱动器驱动，所述电源驱动器旨在在电源输出端提供电源电压VDD。 该方法包括将减速PWM信号施加到桥式驱动器以减速DC电动机，并且如果电源输出端的电压超过较高的第一电压阈值，则控制电桥驱动器使得电动机引起的反向电流降低 比VDD。 根据示例性实施例，该方法包括以下步骤：如果电源输出处的电压低于低于第一电压阈值的第二电压阈值，则终止桥式驱动器的控制，使得电动机引起的后退 电流减少。

公开(公告)号：US20120098344A1

公开(公告)日：2012-04-26

申请号：US13318730

申请日：2009-07-10

申请人： Hendrik Johannes Bergveld ,  Franciscus A. C. M. Schoofs ,  Gian Hoogzaad

发明人： Hendrik Johannes Bergveld ,  Franciscus A. C. M. Schoofs ,  Gian Hoogzaad

IPC分类号： H02J9/00

CPC分类号： H02J7/35 ,  H01L31/02021 ,  H02S40/32 ,  Y02E10/566 ,  Y10T307/615 ,  Y10T307/62

摘要： The present invention relates to the field of photovoltaic systems with solar cell (s) or modules having insolation differences or mismatch. Each solar module is formed by placing a large number of solar cells in series. The PV system is then formed by placing a number of solar modules in series in a string and sometimes by placing multiple strings of series-connected solar modules in parallel, depending on the desired output voltage and power range of the PV system. In practical cases, differences will exist between output powers of the solar cells in the various modules, e.g. due to (part of) the modules being temporarily shaded, pollution on one or more solar cells, or even spread in solar-cell behaviour that may become worse during aging. Due to the current-source-type behaviour of solar cells and their series connection these differences will lead to a relatively large drop in output power coming from the PV system. This invention addresses this problem by adding DC-DC converters (803) on a single or multiple solar-cell level that source or sink difference currents thereby increasing the output power of the complete PV system. In embodiments, the efficiency of photovoltaic systems with solar cell (s) or modules is improved by compensating for output-power loss caused by insolation difference and mismatch.

摘要翻译： 本发明涉及具有太阳能电池或具有日照差异或不匹配的模块的光伏系统领域。 每个太阳能模块通过串联放置大量太阳能电池而形成。 然后通过将多个太阳能模块串联放置在串中并且有时根据PV系统的期望的输出电压和功率范围并联放置多串串联的太阳能电池组件来形成PV系统。 在实际情况下，在各种模块中的太阳能电池的输出功率之间将存在差异。 由于（部分）模块暂时阴影，对一个或多个太阳能电池造成污染，甚至在太阳能电池行为中蔓延，在老化过程中可能会变得更糟。 由于太阳能电池的电流型行为及其串联，这些差异将导致来自光伏系统的输出功率相对较大的下降。 本发明通过在单个或多个太阳能电池级别上添加DC-DC转换器（803）来解决这个问题，源或汇差电流从而增加了整个PV系统的输出功率。 在实施例中，通过补偿由日照差和失配引起的输出功率损耗来提高具有太阳能电池或模块的光伏系统的效率。

公开(公告)号：US08030861B2

公开(公告)日：2011-10-04

申请号：US12307283

申请日：2007-07-03

申请人： Gian Hoogzaad

发明人： Gian Hoogzaad

IPC分类号： H02P3/14 ,  H02P23/00

CPC分类号： H02P23/20

摘要： The invention is directed to a method for controlling a deceleration process of a DC motor (20), wherein the DC motor (20) is driven by a bridge driver (18) coupled to a power supply (12) intended to provide a supply voltage VDD at a power supply output (14), the method comprising the following steps: applying a deceleration PWM signal to the bridge driver (18) for decelerating the DC motor (20), and controlling the bridge driver (18) such that a motor-induced back current is reduced, if the voltage at the power supply output (14) exceeds a voltage threshold which is higher than VDD. In accordance with the invention the step of controlling the bridge driver (18) such that a motor-induced back current is reduced, if the voltage at the power supply output (14) exceeds a voltage threshold which is higher than VDD comprises: if the voltage at the power supply output exceeds the voltage threshold, changing stepwise the pulse width of the deceleration PWM signal in a first direction until the voltage at the power supply (14) output reaches or falls below the voltage threshold, and then, if the voltage at the power supply output (14) has fallen below the voltage threshold, changing stepwise the pulse width of the deceleration PWM signal in a second direction opposite to the first direction until the voltage at the power supply output (14) again reaches or exceeds the voltage threshold. The invention is also directed to a controller suitable to carry out the above method.

摘要翻译： 本发明涉及一种用于控制直流电动机（20）的减速过程的方法，其中直流电动机（20）由连接到电源（12）的桥式驱动器（18）驱动，所述电源驱动器（18）旨在提供电源电压 VDD处于电源输出端（14），该方法包括以下步骤：向桥式驱动器（18）施加减速PWM信号，以减速直流电动机（20），并控制桥式驱动器（18），使电动机 如果电源输出（14）的电压超过VDD的电压阈值，则降低反向电流。 如果电源输出（14）处的电压超过高于VDD的电压阈值，则根据本发明，控制电桥驱动器（18）的步骤使得电机引起的反向电流降低，如果 电源输出端的电压超过电压阈值，逐步改变减速PWM信号的脉冲宽度，直到电源（14）输出端的电压达到或低于电压阈值，然后如果电压 在电源输出（14）下降到低于电压阈值的情况下，在与第一方向相反的第二方向上逐步改变减速PWM信号的脉冲宽度，直到电源输出（14）的电压再次达到或超过 电压阈值。 本发明还涉及一种适用于执行上述方法的控制器。

公开(公告)号：US20100181923A1

公开(公告)日：2010-07-22

申请号：US12669368

申请日：2008-07-16

申请人： Gian Hoogzaad

发明人： Gian Hoogzaad

IPC分类号： H05B39/00

CPC分类号： H05B33/083

摘要： A LED string is divided into segments that each have a bypass-switch and a driver for the bypass-switch. The driver is powered by a supply voltage locally generated from the forward-voltages of the LEDs of the segment.

摘要翻译： LED串被分成各个段，每个段具有旁路开关和用于旁路开关的驱动器。 驱动器由从段的LED的正向电压局部产生的电源电压供电。

公开(公告)号：US07737817B2

公开(公告)日：2010-06-15

申请号：US10517106

申请日：2003-05-21

申请人： Hans Paul Tuinhout ,  Gian Hoogzaad ,  Maarten Vertregt

发明人： Hans Paul Tuinhout ,  Gian Hoogzaad ,  Maarten Vertregt

IPC分类号： H01C7/22

CPC分类号： H01L27/0802

摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.

摘要翻译： 本发明涉及一种电阻网络（2），例如电阻梯形网络，至少包括一个电阻体（4），该电阻器体（4）至少设置有位于第一抽头和第二抽头之间的抽头（6）的至少一列 抽头，其中在使用中，至少两个抽头可以与相应的第一和第二参考输入电位源连接，并且其中所述至少一列抽头的每个抽头可以用于经由接触区域输出输出电位，所述接触区域 与所述有关抽头连接，其中所述电阻体（4）包括多个电阻子体（5），其中每个电阻子体（5）与抽头（8）的列（6）连接，以及 其中通过与电阻子体（5）连接的抽头（8）的电连接来建立电阻子体（5）之间的唯一电连接。 此外，本发明涉及一种用于制造诸如电阻梯形网络的电阻网络（2）的方法。

公开(公告)号：USRE41371E1

公开(公告)日：2010-06-08

申请号：US10923562

申请日：2000-07-06

申请人： Hendrik Van der Ploeg ,  Gian Hoogzaad

发明人： Hendrik Van der Ploeg ,  Gian Hoogzaad

IPC分类号： H03M1/10

CPC分类号： H03M1/0607 ,  H03M1/165

摘要： An analog to digital converter comprises a first stage for developing a set of most significant bits from an analog input signal and for producing analog residue signals (RA, RB) corresponding to respective differences between the analog input signal and threshold values directly above and below, respectively, the analog input signal, and a second stage (AMPA, AMPB, ADC2) for developing a set of lesser significant bits from the analog residue signals (RA, RB). According to the invention, the analog residue signals (RA, RB) are reversed (CA, CB). An offset detection unit (COD, DOD) coupled to the second stage (AMPA, AMPB, ADC2) retrieves offset data representative of offset errors, and an offset correction unit (AD1, AD2, OCA, OCB) corrects the offset errors on the basis of the offset data.

摘要翻译： 模数转换器包括用于从模拟输入信号开发一组最高有效位并用于产生对应于模拟输入信号和直接在上下的阈值之间的相应差异的模拟残留信号（RA，RB）的第一级， 分别为模拟输入信号，以及用于从模拟残留信号（RA，RB）开发一组较低有效位的第二级（AMPA，AMPB，ADC2）。 根据本发明，模拟残留信号（RA，RB）被反转（CA，CB）。 耦合到第二级（AMPA，AMPB，ADC2）的偏移检测单元（COD，DOD）检索表示偏移误差的偏移数据，并且偏移校正单元（AD1，AD2，OCA，OCB）在基础上校正偏移误差 的偏移数据。

公开(公告)号：US20090310269A1

公开(公告)日：2009-12-17

申请号：US12373792

申请日：2007-07-10

申请人： Georg Sauerlander ,  Gian Hoogzaad

发明人： Georg Sauerlander ,  Gian Hoogzaad

IPC分类号： H02H3/00

CPC分类号： H05B33/083 ,  H05B33/0824

摘要： Arrangements (1) are provided with electrical elements (11,21) for, in a feeding mode, receiving feeding signals and, in a non-feeding mode, not receiving the feeding signals, and with circuits (12,22) for, in the feeding mode, detecting malfunctions of the electrical elements (11,21). The circuits (12,22) comprise active switches (13,23) for, in response to detection results, deactivating the electrical elements (11,21) in both modes, in other words in the feeding mode as well as the non-feeding mode. The electrical elements (11,21) for example comprise light emitting diodes, incandescent lights or loudspeakers etc. The active switches (13,23) for example comprise bistable micro-relays or semiconductor switches such as non-volatile power semiconductor switches such as one time programmable flash power MOSFETs etc. Preferably, the arrangements (1) are integrated arrangements.

摘要翻译： 安排（1）设置有电气元件（11,21），用于在馈电模式下接收馈送信号，并且在非馈电模式下，不接收馈送信号，并且具有电路（12,22），用于 馈送模式，检测电气元件（11,21）的故障。 电路（12,22）包括有源开关（13,23），用于响应于检测结果，在两种模式下，换句话说，在馈电模式以及不馈电中，电激励元件（11,21） 模式。 电气元件（11,21）例如包括发光二极管，白炽灯或扬声器等。有源开关（13,23）例如包括双稳态微型继电器或诸如非易失性功率半导体开关的半导体开关，例如一个 时间可编程闪存功率MOSFET等。优选地，布置（1）是集成布置。

公开(公告)号：US06489814B2

公开(公告)日：2002-12-03

申请号：US09817969

申请日：2001-03-27

申请人： Gian Hoogzaad ,  Eise Carel Dijkmans ,  Raf Lodewijk Jan Roovers

发明人： Gian Hoogzaad ,  Eise Carel Dijkmans ,  Raf Lodewijk Jan Roovers

IPC分类号： G11C2702

CPC分类号： G11C27/026

摘要： A track and hold amplifier for use in analog/digital-converters comprises, in succession, an input buffer, a pn-junction switch and hold a capacitor. A feedback is provided between the hold capacitor and the input buffer and a second pn-junction switch is provided to disable the feedback during the hold mode.

摘要翻译： 用于模拟/数字转换器的轨道和保持放大器包括输入缓冲器，pn结开关和保持电容器。 在保持电容器和输入缓冲器之间提供反馈，并且提供第二pn结开关以在保持模式期间禁止反馈。

公开(公告)号：US06437717B1

公开(公告)日：2002-08-20

申请号：US09787185

申请日：2001-03-15

申请人： Hendrik Van der Ploeg ,  Gian Hoogzaad

发明人： Hendrik Van der Ploeg ,  Gian Hoogzaad

IPC分类号： H03M110

CPC分类号： H03M1/0607 ,  H03M1/165

摘要： An analog to digital converter comprises a first stage for developing a set of most significant bits from an analog input signal and for producing analog residue signals (RA, RB) corresponding to respective differences between the analog input signal and threshold values directly above and below, respectively, the analog input signal, and a second stage (AMPA, AMPB, ADC2) for developing a set of lesser significant bits from the analog residue signals (RA, RB). According to the invention, the analog residue signals (RA, RB) are reversed (CA, CB). An offset detection unit (COD, DOD) coupled to the second stage (AMPA, AMPB, ADC2) retrieves offset data representative of offset errors, and an offset correction unit (AD1, AD2, OCA, OCB) corrects the offset errors on the basis of the offset data.

摘要翻译： 模数转换器包括用于从模拟输入信号开发一组最高有效位并用于产生对应于模拟输入信号和直接在上下的阈值之间的相应差异的模拟残留信号（RA，RB）的第一级， 分别为模拟输入信号，以及用于从模拟残留信号（RA，RB）开发一组较低有效位的第二级（AMPA，AMPB，ADC2）。 根据本发明，模拟残留信号（RA，RB）被反转（CA，CB）。 耦合到第二级（AMPA，AMPB，ADC2）的偏移检测单元（COD，DOD）检索表示偏移误差的偏移数据，并且偏移校正单元（AD1，AD2，OCA，OCB）在基础上校正偏移误差 的偏移数据。

公开(公告)号：US06323700B2

公开(公告)日：2001-11-27

申请号：US09746026

申请日：2000-12-21

申请人： Gian Hoogzaad

发明人： Gian Hoogzaad

IPC分类号： H03K300

CPC分类号： G11C27/026

摘要： The present invention relates to an input buffer for a switched emitter follower-like track-and-hold amplifier comprising an input stage with an input transistor (Q1), a first diode (Q2, Q2b), a cathode side of which first diode (Q2, Q2b) is connected to an emitter of the input transistor (Q1), a first current source (4) between on the one hand the junction between the cathode of the first diode (Q2, Q2b) and the emitter of the input transistor (Q1) and on the other hand a first supply voltage line (2), an anode of the first diode (Q2, Q2b) being connected to a track-and-hold controlled emitter follower (6). The first current source (4) is a non-switched constant current source, and a second current source (M1) is connected between a collector of the input transistor (Q1) and a second supply voltage (3). A second transistor (M2, M2b) comprising a control electrode, a current input electrode and a current output electrode is connected with the control electrode to the junction (n1) between the collector of the input transistor (Q1) and the second current source (M1), with the current input electrode to the second supply voltage (3) and with the current output electrode to the anode of the first diode (Q2, Q2b).

摘要翻译： 本发明涉及一种用于开关式射极跟踪器跟踪保持放大器的输入缓冲器，包括：具有输入晶体管（Q1）的输入级，第一二极管（Q2，Q2b），其第一二极管 Q2，Q2b）连接到输入晶体管（Q1）的发射极，第一电流源（4）一方面是第一二极管（Q2，Q2b）的阴极与输入晶体管的发射极 （Q1），另一方面是第一电源电压线（2），第一二极管（Q2，Q2b）的阳极连接到跟踪和保持控制的射极跟随器（6）。 第一电流源（4）是非开关恒流源，并且第二电流源（M1）连接在输入晶体管（Q1）的集电极和第二电源电压（3）之间。 包括控制电极，电流输入电极和电流输出电极的第二晶体管（M2，M2b）与控制电极连接到输入晶体管（Q1）和第二电流源（Q1）的集电极之间的结（n1） M1），其中电流输入电极到第二电源电压（3），并且电流输出电极连接到第一二极管（Q2，Q2b）的阳极。