公开(公告)号：US20120032722A1

公开(公告)日：2012-02-09

申请号：US12881434

申请日：2010-09-14

申请人： Jan MULDER

发明人： Jan MULDER

IPC分类号： H03L5/00

CPC分类号： H03F3/45475 ,  H03F3/45192 ,  H03F3/45928 ,  H03F2203/45048 ,  H03F2203/45138 ,  H03F2203/45586 ,  H03M1/1023 ,  H03M1/165

摘要： An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN−), a positive differential output (VOUT+), and a negative differential output (VOUT−). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT−. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT− when VIN+ and VIN− are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT−, respectively.

摘要翻译： 提供了一种装置，方法和系统来校准放大器中的偏移。 该装置可以包括放大器，电压控制单元，比较器和处理单元。 放大器可以有四个端子：正差分输入（VIN +），负差分输入（VIN-），正差分输出（VOUT +）和负差分输出（VOUT-））。 电压控制单元可配置为调节VOUT +上的第一电压和VOUT-上的第二电压。 当VIN +和VIN-耦合到公共电压时，比较器可以配置为将VOUT +上的第一个电压与VOUT-上的第二个电压进行比较。 此外，处理单元可以被配置为基于VOUT +和VOUT-上的第一和第二电压的比较来向电压控制单元提供控制信号。

公开(公告)号：US07760125B2

公开(公告)日：2010-07-20

申请号：US12026901

申请日：2008-02-06

申请人： Yoshiaki Shimizu ,  Hisao Suzuki ,  Kenji Ito ,  Masashi Kijima

发明人： Yoshiaki Shimizu ,  Hisao Suzuki ,  Kenji Ito ,  Masashi Kijima

IPC分类号： H03M1/36

CPC分类号： H03M1/0675 ,  H03M1/08 ,  H03M1/165 ,  H03M1/168 ,  H03M1/366 ,  H03M1/42 ,  H03M1/765

摘要： An A/D conversion circuit including a plurality of resistor elements connected in series between a low-potential power supply and a high-potential power supply. The A/D conversion circuit includes a plurality of comparators that compare a reference voltage divided by each of the resistor elements with an analog input voltage, the comparators having a sample-and-hold function for holding a sampled analog input voltage. The plurality of comparators also include a high-order bit comparator and a low-order bit comparator having different sampling sources. The high-order bit comparator may be configured to compare the analog input voltage and one of the reference voltages to obtain a determination result. The low-order bit comparator may old the analog voltage from the time that the low-order bit comparator retrieves the analog input voltage until the low-order bit comparator performs comparison.

摘要翻译： 一种A / D转换电路，包括串联连接在低电位电源和高电位电源之间的多个电阻元件。 A / D转换电路包括将由每个电阻元件划分的参考电压与模拟输入电压进行比较的多个比较器，比较器具有用于保持采样的模拟输入电压的采样保持功能。 多个比较器还包括具有不同采样源的高位比较器和低位比较器。 高位比较器可以被配置为比较模拟输入电压和参考电压之一以获得确定结果。 低位比较器可以从低位比较器检索模拟输入电压直到低位比较器执行比较时的模拟电压为老。

公开(公告)号：US20090015450A1

公开(公告)日：2009-01-15

申请号：US12026901

申请日：2008-02-06

申请人： Yoshiaki Shimizu ,  Hisao Suzuki ,  Kenji Ito ,  Masashi Kijima

发明人： Yoshiaki Shimizu ,  Hisao Suzuki ,  Kenji Ito ,  Masashi Kijima

IPC分类号： H03M1/00 ,  H03M1/76

CPC分类号： H03M1/0675 ,  H03M1/08 ,  H03M1/165 ,  H03M1/168 ,  H03M1/366 ,  H03M1/42 ,  H03M1/765

摘要： A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

摘要翻译： 用于以高速执行D / A转换的D / A转换电路。 D / A转换电路包括连接在低电位电源和高电位电源之间的多个电阻元件的电阻串。 多个第一开关组连接到电阻元件之间的连接节点，用于选择性地输出连接节点处的电压。 第一交换机组的交换机的输出共同连接到对应的一个节点。 多个节点通过第二开关组连接到D / A转换电路的输出端。 第一开关组的预定开关并联连接到第三开关以向节点施加电压。

公开(公告)号：US06720901B2

公开(公告)日：2004-04-13

申请号：US10454694

申请日：2003-06-05

申请人： Hiroyuki Nakamoto

发明人： Hiroyuki Nakamoto

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： An interpolation circuit for generating interpolation and extrapolation differential voltages to a first and second differential input voltages, comprises a first and second differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal and their respective non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the non-inverted output terminals of the first and second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array. The interpolation circuit further comprises a third voltage dividing element array disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, so that at least a pair of extrapolation differential voltages are generated from nodes in the third voltage dividing element array.

摘要翻译： 一种用于产生对第一和第二差分输入电压的插值和外插差分电压的内插电路，包括分别用于输入第一和第二差分输入电压的第一和第二差分放大器，并且用于分别在它们的反相输出 端子及其各自的非倒置端子。 内插电路还包括设置在第一和第二差分放大器的非反相输出端之间的第一分压元件阵列和设置在第一和第二差分放大器的反相输出端之间的第二分压元件阵列，使得 内插差分电压由第一分压元件阵列中的节点和第二分压元件阵列中的节点产生。 插值电路还包括设置在第一差分放大器的反相输出端和第二差分放大器的非反相输出端之间的第三分压元件阵列，使得至少一对外推差分电压从 第三分压元件阵列。

公开(公告)号：US06714886B2

公开(公告)日：2004-03-30

申请号：US10207470

申请日：2002-07-29

申请人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

发明人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

摘要翻译： 一种用于校准具有包括Σ-Δ转换器，计数器，存储器，调整逻辑，DAC，一对补偿电容器和一对电流 - 电压（I / V）转换器的补偿输入的放大器的补偿系统。 转换器将偏移电压转换为位流。 计数器存储表示输出偏移量的和值。 存储器存储数字偏置值。 调整逻辑基于和值确定调整值，并根据调整值调整存储的数字偏置值。 DAC将数字偏置值转换为差分偏置电流。 补偿电容器将补偿电压施加到放大器的补偿输入。 I / V转换器使用差分偏置电流对补偿电容器充电。 调整逻辑可以使用上限和下限阈值，并且在每个补偿周期内将数字偏置值调整一个LSB​​。

公开(公告)号：US20030151430A1

公开(公告)日：2003-08-14

申请号：US10308775

申请日：2002-12-03

发明人： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

IPC分类号： H03K005/00

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGSnullVT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

摘要翻译： 双泵电路，包括传输门和双电荷泵。 传输门包括一个p沟道晶体管和一个n沟道晶体管，每个具有一个控制端子和一对电流端子，耦合在一个双泵输入端和一个双泵输出端之间。 双电荷泵包括第一和第二泵电路，其中每个泵电路耦合到双泵输入和相应的一个传输栅晶体管的控制端。 每个泵电路通过维持VGS-VT恒定而使其对应的传输门晶体管的操作线性化。 双泵电路用于包括至少一个双泵采样电路，至少一个采样电容器和用于控制输入信号采样定时的控制电路的跟踪和保持电路。 每个双泵采样电路包括传输门和双电荷泵。

公开(公告)号：US5841389A

公开(公告)日：1998-11-24

申请号：US833965

申请日：1997-04-11

申请人： Norihide Kinugasa ,  Mitsuhiko Otani ,  Katsumi Hironaka ,  Shinichi Ogita

发明人： Norihide Kinugasa ,  Mitsuhiko Otani ,  Katsumi Hironaka ,  Shinichi Ogita

IPC分类号： H03M1/16 ,  H03M1/36

CPC分类号： H03M1/165 ,  H03M1/365

摘要： Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.L are not changed by the voltage V.sub.IN of the input analog signal. Consequently, a settling time can be shortened more than in the prior art.

摘要翻译： 提供了一种两级并行A / D转换器，其能够以比现有技术更高的速度运行并且容易地执行高位数据的校正。 基于第二差分放大器的电压范围的中值电压VM来放大用于低位转换的电压范围的上限电压VH，并且将放大的电压设置为用于较低位转换的高电平参考电压SUBH 。 电压范围的下限电压VL由第三差分放大器基于中值电压VM放大，放大电压被设定为低电平基准电压SUBL用于低位转换。 输入模拟信号的电压VIN通过第一差分放大器基于电压VM放大，并且从电压SUBH和所获得的电压SUBIN占据的电压SUBL之间的位置获得低位数据。 电压SUBH和SUBL不会被输入模拟信号的电压VIN改变。 因此，与现有技术相比，可以缩短建立时间。

公开(公告)号：US4665326A

公开(公告)日：1987-05-12

申请号：US816676

申请日：1986-01-03

申请人： John C. Domogalla

发明人： John C. Domogalla

IPC分类号： H03M1/00 ,  H03K5/24 ,  H03K5/153

CPC分类号： H03M1/165 ,  H03M1/1023

摘要： A voltage comparator for an analog to digital converter is provided which includes several differential amplifier stages connected in cascade that determine the existence of a voltage difference between the two input signals and amplify this voltage difference successively. The comparator further includes offset correction voltage circuits which are connected to each differential amplifier stage and allow for the correction of errors caused by the mismatching of the devices internal to each of the differntial amplifier stages.

摘要翻译： 提供了一种用于模数转换器的电压比较器，其包括级联连接的几个差分放大器级，以确定两个输入信号之间的电压差的存在并且连续地放大该电压差。 比较器还包括偏移校正电压电路，其连接到每个差分放大器级，并允许校正由每个差分放大器级内部的器件的失配引起的误差。

公开(公告)号：US2946013A

公开(公告)日：1960-07-19

申请号：US67134857

申请日：1957-07-11

申请人： ATOMIC ENERGY AUTHORITY UK

发明人： OLIVER DEIGHTON MICHAEL

IPC分类号： G01R19/04 ,  H03M1/00

CPC分类号： G01R19/04 ,  H03M1/165

公开(公告)号：US08884803B2

公开(公告)日：2014-11-11

申请号：US13874882

申请日：2013-05-01

申请人： Fujitsu Limited

发明人： Yanfei Chen

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/16

CPC分类号： H03M1/12 ,  H03M1/1225 ,  H03M1/165

摘要： An analog-digital converter apparatus includes a plurality of AD converters connected in series, each AD converter to convert an analog signal received by a first AD converter, at least one of the AD converters including: a residual signal generator that generates a first residual signal, the first residual signal being a difference between the analog signal or one of two residual signals amplified and output by a preceding AD converter and a first reference signal, and a second residual signal, the second residual signal being a difference between the analog signal or one of the two residual signals and a second reference signal; and an amplifier that amplifies and outputs the first residual signal to a subsequent AD converter at a first timing and amplifies and outputs the second residual signal to the subsequent AD converter at a second timing.

摘要翻译： 模数转换器装置包括串联连接的多个AD转换器，每个AD转换器转换由第一AD转换器接收的模拟信号，所述AD转换器中的至少一个包括：残差信号发生器，其生成第一残余信号 所述第一残差信号是所述模拟信号或由前一AD转换器放大和输出的两个残余信号中的一个与第一参考信号之间的差，以及第二残差信号，所述第二残差信号是所述模拟信号或 两个残差信号中的一个和第二参考信号; 以及放大器，其在第一定时将第一残差信号放大并输出到后续的AD转换器，并在第二定时将第二残留信号放大并输出到后续的AD转换器。