-
公开(公告)号：US06631430B1
公开(公告)日：2003-10-07
申请号：US09473113
申请日：1999-12-28
IPC分类号： G06F1200
CPC分类号： G06F13/385 , Y10S370/912
摘要： Receiving bytes of data from a media device includes issuing N consecutive requests, each for M-bytes, to the media device and receiving N−1 responses of M bytes of data from the media device.
摘要翻译： 从媒体设备接收数据字节包括向媒体设备发送N个连续请求，每个M个字节用于M字节，并从媒体设备接收M字节数据的N-1个响应。
-
公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
-
公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
-
24.发明授权公开(公告)号：US06532509B1
公开(公告)日：2003-03-11
申请号：US09470541
申请日：1999-12-22
IPC分类号： G06F1314
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
-
公开(公告)号：US07546444B1
公开(公告)日：2009-06-09
申请号：US10070091
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD—3 . . . THREAD—0). The processor maintains execution threads (THREAD—3 . . . THREAD—0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD—3 . . . THREAD—0).
摘要翻译： 描述了基于并行硬件的多线程处理器。 该处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文（THREAD-3，...，THREAD-0）的多个微启动器。 处理器维护执行线程（THREAD-3 ... THREAD-0）访问组织成多个相对可寻址的寄存器窗口的寄存器集合，这些寄存器窗口相对于每个线程可访问（THREAD-3 ... THREAD-0）。
-
公开(公告)号：US07191321B2
公开(公告)日：2007-03-13
申请号：US10643438
申请日：2003-08-19
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器参考是针对偶数存储体还是存储器的奇数存储器排序存储器引用，以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
-
27.发明授权Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch 失效用于维护多个以太网端口交换机的接收数据包排序的端口阻塞技术公开(公告)号：US06976095B1
公开(公告)日：2005-12-13
申请号：US09476303
申请日：1999-12-30
CPC分类号： G06F9/485 , G06F9/4881 , H04L49/3009
摘要： A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from ports in segments and each segment is assigned to one of the program threads. Ordering of segments within packets, and between packets from the same port, is maintained by a scheduler program thread. The scheduler program thread blocks a new assignment of the previously assigned port to a program thread until the program thread to which the port was previously assigned has indicated that it has completed the processing of the segment from that port.
摘要翻译： 具有多个处理元件的网络处理器，每个处理元件支持多个同时进行的程序线程，可以访问接口中的共享资源。 分组数据从段中的端口接收，并且每个段被分配给程序线程之一。 在同一个端口的数据包之间以及数据包之间进行订阅，由调度程序线程维护。 调度器程序线程将先前分配的端口的新分配阻塞到程序线程，直到先前分配了端口的程序线程已经指示已经完成了该端口的段的处理。
-
28.发明授权Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section 有权并行处理器，功能管道提供编程引擎，支持多个上下文和关键部分公开(公告)号：US06934951B2
公开(公告)日：2005-08-23
申请号：US10053172
申请日：2002-01-17
申请人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
发明人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.
摘要翻译： 一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。 该系统和方法包括并行处理器，其分配用于处理数据的系统功能，所述系统功能包括支持多个上下文的编程引擎，所述编程引擎被布置为通过在所述编程引擎之间传递功能数据的功能流水线控制单元提供功能
-
公开(公告)号：US06668317B1
公开(公告)日：2003-12-23
申请号：US09387046
申请日：1999-08-31
IPC分类号： G06F948
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
-
公开(公告)号：US07610451B2
公开(公告)日：2009-10-27
申请号：US10057738
申请日：2002-01-25
CPC分类号： G06F9/3824 , G06F9/3851
摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.
摘要翻译： 一种用于在编程代理和存储器资源之间传送数据的方法。 该方法包括在处理代理和存储器资源之间传送数据，指定存储器资源，用于经由具有仲裁使用推送总线的多个源的推送总线将数据推送到处理代理，以及指定用于接收的存储器资源 来自处理代理的数据经由具有仲裁使用拉总线的多个目的地的拉总线。
-
-
-
-
-
-
-
-
-
搜索结果
102 条记录 (耗时 0.032 秒)
