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公开(公告)号：US06560667B1
公开(公告)日：2003-05-06
申请号：US09473112
申请日：1999-12-28
IPC分类号： G06F1318
CPC分类号： G06F13/1642
摘要： A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, such that the arbiter services a same queue until the chaining bit is cleared.
摘要翻译： 用于随机存取存储器的控制器具有控制逻辑，包括检测未完成存储器引用状态的仲裁器。 控制器从存储器引用的多个队列中的一个队列中选择存储器引用。 控制逻辑响应于存储器参考链接位，当设置允许连续存储器引用的特殊处理时，仲裁器服务相同的队列，直到链接位被清除。
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公开(公告)号：USRE41849E1
公开(公告)日：2010-10-19
申请号：US11159427
申请日：2005-06-22
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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公开(公告)号：US06681300B2
公开(公告)日：2004-01-20
申请号：US09969436
申请日：2001-10-02
IPC分类号： G06F1200
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.
摘要翻译： 管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取 锁定未命中队列至少包含一个读锁定存储器引用请求。
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公开(公告)号：US07111296B2
公开(公告)日：2006-09-19
申请号：US10615280
申请日：2003-07-08
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用 被读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。
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公开(公告)号：US06587906B2
公开(公告)日：2003-07-01
申请号：US10339221
申请日：2003-01-09
IPC分类号： G06F1300
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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7.发明授权公开(公告)号：US06532509B1
公开(公告)日：2003-03-11
申请号：US09470541
申请日：1999-12-22
IPC分类号： G06F1314
CPC分类号： G06F9/3851
摘要： A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
摘要翻译： 描述了用于仲裁命令请求的并行多线程处理器系统和技术。 该系统包括多个微引擎，多个共享系统资源和全局命令仲裁器。 全局命令仲裁器使用基于共享系统资源和命令类型的命令请求协议来授予或拒绝共享资源的微引擎命令请求。
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公开(公告)号：US06324624B1
公开(公告)日：2001-11-27
申请号：US09473798
申请日：1999-12-28
IPC分类号： G06F1318
CPC分类号： G06F9/52
摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.
摘要翻译： 管理对随机存取存储器的存储器访问包括获取读锁定存储器引用请求并将读锁定存储器引用请求放置在读锁定未命中队列的末尾，如果（1）读锁定存储器引用请求正在请求访问解锁的存储器位置 和（2）读取锁定未命中队列至少包含一个读取锁定存储器引用请求。
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公开(公告)号：US07191321B2
公开(公告)日：2007-03-13
申请号：US10643438
申请日：2003-08-19
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器参考是针对偶数存储体还是存储器的奇数存储器排序存储器引用，以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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公开(公告)号：US06668317B1
公开(公告)日：2003-12-23
申请号：US09387046
申请日：1999-08-31
IPC分类号： G06F948
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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