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21.发明申请公开(公告)号：US20180278444A1
公开(公告)日：2018-09-27
申请号：US15992519
申请日：2018-05-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Henry Wong , Davide Tonietto
CPC classification number: H04L25/03885 , H04L5/006
Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
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22.发明授权公开(公告)号：US09712349B1
公开(公告)日：2017-07-18
申请号：US15071522
申请日：2016-03-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Henry Wong , Davide Tonietto
CPC classification number: H04L25/03885 , H04L5/006
Abstract: A system and method for Feed Forward. Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
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公开(公告)号：US20170147251A1
公开(公告)日：2017-05-25
申请号：US15425466
申请日：2017-02-06
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Jian Zhang
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/0685 , H04L47/50 , H04L49/901
Abstract: Embodiments of the present invention disclose a queue management method. The method includes writing a PD queue to a DRAM, where the PD queue includes multiple PDs, and the multiple PDs correspond one-to-one to multiple packets included in a first packet queue. The method also includes writing at least one PD in the PD queue to an SRAM, where the at least one PD includes a queue head of the PD queue. Correspondingly, the embodiments of the present invention further disclose a queue management apparatus.
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公开(公告)号：US12237954B2
公开(公告)日：2025-02-25
申请号：US18188251
申请日：2023-03-22
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Abstract: This application discloses example data encoding methods, data decoding methods, and communication apparatuses. One example data encoding method includes generating M encoding units and distributing the M encoding units to N transmission channels. The M encoding units are obtained by encoding L frames. The M encoding units include at least one first-type unit. A first-type unit of the at least one first-type unit includes a first identifier. The first identifier indicates a start location that is in the first-type unit and that is of a frame header of a first frame in the L frames. M, N, and L are integers greater than or equal to 1.
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25.发明授权公开(公告)号：US11870124B2
公开(公告)日：2024-01-09
申请号：US17244741
申请日：2021-04-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Dajun Zang , Cuicui Wang , Daochun Mo , Yuchun Lu , Linchun Wang
Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.
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Patent Agency Ranking
公开(公告)号：US11539461B2
公开(公告)日：2022-12-27
申请号：US17100394
申请日：2020-11-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Lin Ma , Liang Li , Yongyao Li , Shengyu Shen
Abstract: Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.
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公开(公告)号：US20210075540A1
公开(公告)日：2021-03-11
申请号：US17100394
申请日：2020-11-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Lin Ma , Liang Li , Yongyao Li , Shengyu Shen
IPC: H04L1/00
Abstract: Embodiments of this application disclose an encoding method and a related device. The method includes: receiving a to-be-encoded code block whose length is L, where L is a positive integer; and encoding the to-be-encoded code block to obtain a forward error correction FEC code, where a valid information length K of the FEC code is an integer multiple of a largest prime factor of L, and a total length N of the FEC code is a sum of K and a product of 2 and an error correction capability T of the FEC code. According to the embodiments of this application, it can be ensured that an FEC codeword satisfies a requirement for a low latency and a high gain.
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公开(公告)号：US10248350B2
公开(公告)日：2019-04-02
申请号：US15425466
申请日：2017-02-06
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Jian Zhang
IPC: G06F3/06 , H04L12/863 , H04L12/879
Abstract: Embodiments of the present invention disclose a queue management method. The method includes writing a PD queue to a DRAM, where the PD queue includes multiple PDs, and the multiple PDs correspond one-to-one to multiple packets included in a first packet queue. The method also includes writing at least one PD in the PD queue to an SRAM, where the at least one PD includes a queue head of the PD queue. Correspondingly, the embodiments of the present invention further disclose a queue management apparatus.
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公开(公告)号：US10129049B2
公开(公告)日：2018-11-13
申请号：US15436496
申请日：2017-02-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu
IPC: H04L12/413 , H04L29/12 , H04L12/721
Abstract: Embodiments provide a data transmission method, including: receiving, by a receiving circuit in a media access controller, N packets; generating, by a distributing circuit, a first data block and a second data block, where the first data block includes a first set, and the second data block includes a second set; distributing the first data block to a first circuit, and distributing the second data block to a second circuit; converting, by the first circuit, the first data block into first data, and converting, by the second circuit, the second data block into second data; and sending, by the first circuit, the first data through a first channel, and sending, by the second circuit, the second data through a second channel. In addition, another method and a corresponding media access controller are further provided. The foregoing technical solution helps reduce circuit resources occupied by an Ethernet interface.
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30.发明授权公开(公告)号：US10116419B2
公开(公告)日：2018-10-30
申请号：US15411669
申请日：2017-01-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Liang Li , Suping Zhai , Dajun Zang
Abstract: The present embodiments provide a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system. The method includes receiving data, where the data includes N+P consecutive symbols, N consecutive symbols constitute a first data block, and N consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block. The method also includes determining a first iterative item and a second iterative item and determining, according to the s parameter values corresponding to the first data block, s parameter values corresponding to the second data block. Additionally, the method includes determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame.
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