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公开(公告)号：US20240154656A1
公开(公告)日：2024-05-09
申请号：US18514119
申请日：2023-11-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Cuicui Wang , Dajun Zang , Yuchun Lu , Linchun Wang , Daochun Mo
IPC: H04B7/0456 , H04B7/0426
CPC classification number: H04B7/0456 , H04B7/0439
Abstract: A transmission system includes a sending apparatus and N signal channels, where N≥2, and N is an integer. The sending apparatus includes a first apparatus, and the first apparatus is configured to: obtain N to-be-transmitted signals and an encoding coefficient group, where the N to-be-transmitted signals are represented as an N×1 signal matrix X, and the encoding coefficient group is represented as an N×N orthogonal encoding matrix T; process the N to-be-transmitted signals based on the encoding coefficient group to generate N encoded first signals, where the N encoded first signals are represented as a signal matrix Y; and send the N encoded first signals to the N signal channels, where a signal on each signal channel corresponds to an element in a row of the signal matrix Y.
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2.发明申请公开(公告)号：US20170317857A1
公开(公告)日：2017-11-02
申请号：US15651715
申请日：2017-07-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Henry Wong , Davide Tonietto
CPC classification number: H04L25/03885 , H04L5/006
Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
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3.发明公开公开(公告)号：US20240259133A1
公开(公告)日：2024-08-01
申请号：US18427263
申请日：2024-01-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yuchun Lu , Yan Zhuang
IPC: H04L1/00
CPC classification number: H04L1/0042 , H04L1/0003
Abstract: A data transmission method, apparatus, and system are applied to the field of communication technologies. The method includes: performing demultiplexing processing on obtained y first data streams to obtain x second data streams, where the y first data streams are obtained through bit multiplexing processing; mapping the x second data streams at a granularity of n bits to obtain z third data streams; and outputting the z third data streams over an output lane, where y, x, n, and z are all positive integers, and n≥2. The method may be applied to an Ethernet high-speed interface.
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公开(公告)号：US20240045758A1
公开(公告)日：2024-02-08
申请号：US18489276
申请日：2023-10-18
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liang Li , Chun Yuan , Yuchun Lu , Lin Ma , Yongzhi Liu
IPC: G06F11/08
CPC classification number: G06F11/085
Abstract: According to embodiments of the present disclosure, a method and a chip for cyclic code encoding, a circuit component, and an electronic device are provided. The method includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; generating the (N−K) parity symbols based on the first parity sequence and the second parity sequence.
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公开(公告)号：US11438134B2
公开(公告)日：2022-09-06
申请号：US17081632
申请日：2020-10-27
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yuchun Lu
IPC: H04L7/033
Abstract: Embodiments of this application disclose example phase detection methods, phase detection circuits, and clock recovery apparatuses. One example method includes receiving a first signal and deciding a (2M−1) level of the first signal to obtain a decision result, where the first signal is a (2M−1)-level signal, and M is a positive integer. A response amplitude parameter of a transmission channel can then be obtained. Clock phase information in the first signal can then be extracted based on the first signal, the decision result, and the response amplitude parameter. Output clock phase information can then be determined based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods.
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Patent Agency Ranking
公开(公告)号：US11218246B2
公开(公告)日：2022-01-04
申请号：US16889231
申请日：2020-06-01
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yuchun Lu
Abstract: This application provides an error correction method and apparatus, relates to the field of communications technologies, so as to reduce a bit error rate of a decision feedback equalizer (DFE) and improve equalization performance. The method includes: obtaining a decision signal of a DFE; obtaining at least one of an input signal, an equalized output signal, and a difference of the DFE, where the difference is a difference between a level value of the decision signal and a level value of the equalized output signal; determining a symbol location of an end of burst error of the decision signal based on detection of at least one of the decision signal, the equalized output signal, and the difference; and when the symbol location is detected, performing error correction on the decision signal based on the at least one of the input signal, the equalized output signal, and the difference.
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7.发明授权公开(公告)号：US10003481B2
公开(公告)日：2018-06-19
申请号：US15651715
申请日：2017-07-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Henry Wong , Davide Tonietto
CPC classification number: H04L25/03885 , H04L5/006
Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.
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8.发明申请公开(公告)号：US20170134121A1
公开(公告)日：2017-05-11
申请号：US15411669
申请日：2017-01-20
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Liang Li , Suping Zhai , Dajun Zang
CPC classification number: H04L1/0083 , H03M13/333 , H03M13/3746 , H04L1/00 , H04L7/048
Abstract: The present embodiments provide a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system. The method includes receiving data, where the data includes N+P consecutive symbols, N consecutive symbols constitute a first data block, and N consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block. The method also includes determining a first iterative item and a second iterative item and determining, according to the s parameter values corresponding to the first data block, s parameter values corresponding to the second data block. Additionally, the method includes determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame.
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公开(公告)号：US20250023763A1
公开(公告)日：2025-01-16
申请号：US18898884
申请日：2024-09-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yuchun Lu , Weiyu Wang , Huanlu Li , Haiyang Zhang , Liang Li , Qinyu Zhou
IPC: H04L25/03
Abstract: A detection method includes: obtaining a decision feedback equalizer coefficient, where the decision feedback equalizer coefficient includes a tap coefficient; obtaining a decision signal sequence of a decision feedback equalizer; determining a first location of a decision signal of a start of burst error in the decision signal sequence when the tap coefficient is less than or equal to a first preset threshold; and determining a second location of a decision signal of an end of burst error in the decision signal sequence based on the first location.
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10.发明申请公开(公告)号：US20250007647A1
公开(公告)日：2025-01-02
申请号：US18775927
申请日：2024-07-17
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Yuchun Lu , Yan Zhuang
IPC: H04L1/00
Abstract: A data transmission method, apparatus, and system are applied to the field of communication technologies. The method includes: performing demultiplexing processing on obtained y first data streams to obtain x second data streams, where the y first data streams are obtained through bit multiplexing processing; mapping the x second data streams at a granularity of n bits to obtain z third data streams; and outputting the z third data streams over an output lane, where y, x, n, and z are all positive integers, and n≥2. The method may be applied to an Ethernet high-speed interface.
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