公开(公告)号：US20230137572A1

公开(公告)日：2023-05-04

申请号：US17927207

申请日：2020-09-04

Applicant: Seung Hun SHIN ,  Se Yeol CHOI ,  Young Jin LEE

Inventor： Seung Hun SHIN ,  Se Yeol CHOI ,  Young Jin LEE

IPC: A47J27/086 ,  A47J27/08 ,  A47J27/10 ,  H05B6/12

Abstract: A compression type ramen cooker according to an embodiment includes a main frame including side plates formed on both sides thereof, an upper main bar connecting the upper portions of the side plates, and a lower main bar connecting the lower portions of the side plates, a cooking vessel part rotatably mounted on the inner sides of the side plates, a compression chamber mounted above the upper main bar to seal or open the cooking vessel part by moving up and down, an induction heater rotatably mounted on the rear side of the cooking vessel part to heat the cooking vessel part, a ramen discharging part for discharging cooked ramen from the cooking vessel part, and a drain mounted in the lower end of the side plates on both sides to discard the water used for cleaning the cooking vessel part after cooking.

公开(公告)号：US20120007240A1

公开(公告)日：2012-01-12

申请号：US13238570

申请日：2011-09-21

Applicant: Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

Inventor： Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

IPC: H01L23/535

CPC classification number: H01L21/76879 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Abstract translation: 半导体器件的金属布线包括半导体衬底; 绝缘层，设置有形成在所述半导体衬底上的镶嵌图案; 包含在镶嵌图案的表面上形成的RuO 2层的扩散阻挡层和形成在该镶嵌图案的两侧上部的RuO 2层的一部分上的Al沉积抑制层; 以及通过MOCVD法在扩散阻挡层上形成的包括Al的布线金属层，以填充镶嵌图案。

公开(公告)号：US20110298382A1

公开(公告)日：2011-12-08

申请号：US13209122

申请日：2011-08-12

Applicant: Young Jin LEE ,  Byoung Own Min ,  Gil Han Park ,  Grigory Onushkin

Inventor： Young Jin LEE ,  Byoung Own Min ,  Gil Han Park ,  Grigory Onushkin

IPC: H05B37/00

CPC classification number: H05B33/0803 ,  H05B33/0821 ,  Y02B20/342 ,  Y10S362/80 ,  Y10S362/808

Abstract: There is provided an LED driving circuit including: at least one ladder network circuit including: (n+1) number of first branches connected in parallel with one another by n number of first middle junction points between a first junction point and a second junction point, where n denotes an integer satisfying n≧2, (n+1) number of second branches connected in parallel with one another by n number of second middle junction points between the first junction point and the second junction point, the (n+1) number of second branches connected in parallel with the first branches; and n number of middle branches connecting the first and second middle junction points of an identical m sequence to each other, respectively, wherein each of the first and second, and middle branches comprises at least one LED device.

Abstract translation: 提供了一种LED驱动电路，包括：至少一个梯形网络电路，包括：（n + 1）数个第一分支，其在第一连接点和第二连接点之间彼此并联连接n个第一中间连接点 ，其中n表示满足n≥2的整数，（n + 1）个在第一连接点和第二连接点之间由n个第二中间连接点彼此并联连接的第二分支数，第（n + 1）个 ）与第一分支并联连接的第二分支的数量; 以及分别将相同m个序列的第一和第二中间连接点彼此连接的n个中间分支，其中第一和第二和中间分支中的每一个包括至少一个LED装置。

公开(公告)号：US20100193956A1

公开(公告)日：2010-08-05

申请号：US12754776

申请日：2010-04-06

Applicant: Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

Inventor： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

Abstract translation: 公开了一种半导体器件的多层金属布线及其形成方法。 半导体器件的多层金属布线包括下Cu布线和形成为与下Cu布线接触的上Al布线，以及介于下Cu布线和上Al布线之间的扩散阻挡层。 扩散阻挡层由W基层形成。

公开(公告)号：US20090001577A1

公开(公告)日：2009-01-01

申请号：US11939054

申请日：2007-11-13

Applicant: Jeong Tae KIM ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG

Inventor： Jeong Tae KIM ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG

IPC: H01L23/532 ,  H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSixNy layer is interposed between a first Ta-based layer and a second Ta-based layer. A metal line formed in this manner prevents the contact resistance of the metal line from increasing and the leakage current characteristics from degrading, thereby improving the device characteristics and reliability.

Abstract translation: 半导体器件中的金属线包括形成在半导体衬底上的绝缘层。 在绝缘层中形成金属线形成区域。 在金属线形成区域的表面上形成扩散阻挡层，并且形成金属线以填充绝缘层的金属线形成区域。 在金属线和绝缘层之间形成扩散阻挡层。 扩散阻挡层具有其中TaSixNy层介于第一Ta基层和第二Ta基层之间的结构。 以这种方式形成的金属线防止金属线的接触电阻增加，并且漏电流特性降低，从而提高器件特性和可靠性。

公开(公告)号：US20080157368A1

公开(公告)日：2008-07-03

申请号：US11755814

申请日：2007-05-31

Applicant: Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

Inventor： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76846 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.

Abstract translation: 半导体器件的多层金属线具有下金属线和上金属线。 上部金属线包括扩散阻挡层，该扩散阻挡层由第一WN层X 1层，WC x N N层和/ 第二WN 层。

公开(公告)号：US20080146026A1

公开(公告)日：2008-06-19

申请号：US11776905

申请日：2007-07-12

Applicant: Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

Inventor： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

IPC: H01L21/44

CPC classification number: H01L21/76826 ,  H01L21/76838 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in the hole; forming a bit line contact plug in the hole by removing the first metal film and the barrier film so as to expose the interlayer insulation film; carrying out a gas treatment to a surface of the interlayer insulation film including the bit line contact plug so as to promote a growth of metal nucreation; forming a second metal film over the gas treated interlayer insulation film; and forming a bit line in contact with the bit line contact plug by etching the second metal film.

Abstract translation: 半导体存储器件通过：通过蚀刻形成在半导体衬底上的层间绝缘膜来形成孔; 在包括所述孔的表面的所述层间绝缘膜上形成阻挡膜; 在所述阻挡膜上形成第一金属膜以填充所述孔; 通过去除第一金属膜和阻挡膜以形成层间绝缘膜，从而在孔中形成位线接触插塞; 对包含位线接触插塞的层间绝缘膜的表面进行气体处理，以促进金属含量的增长; 在气体处理的层间绝缘膜上形成第二金属膜; 并通过蚀刻第二金属膜形成与位线接触插塞接触的位线。

公开(公告)号：US20110233781A1

公开(公告)日：2011-09-29

申请号：US13152665

申请日：2011-06-03

Applicant: Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

Inventor： Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Abstract translation: 半导体器件中的金属线包括形成在半导体衬底上的绝缘层。 在绝缘层中形成金属线形成区域。 形成金属线以填充绝缘层的金属线形成区域。 并且在金属线和绝缘层之间形成包括非晶态TaBN层的扩散阻挡层。 无定形TaBN层防止铜成分扩散到半导体衬底中，从而改善器件的特性和可靠性。

公开(公告)号：US20100059890A1

公开(公告)日：2010-03-11

申请号：US12619147

申请日：2009-11-16

Applicant: Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

Inventor： Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.

Abstract translation: 描述了具有包括CrxBy的扩散阻挡层的半导体器件的金属线及其形成方法。 半导体器件的金属线包括形成在半导体衬底上的绝缘层。 绝缘层形成有金属线形成区域。 随后在金属线形成区域和绝缘层的表面上形成包括Cr x B y层的扩散阻挡层。 最后形成金属线以填充包含CrxBy层的扩散阻挡层上的绝缘层的金属线形成区域。

公开(公告)号：US20090001580A1

公开(公告)日：2009-01-01

申请号：US11940370

申请日：2007-11-15

Applicant: Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

Inventor： Dong Ha JUNG ,  Seung Jin YEOM ,  Baek Mann KIM ,  Young Jin LEE ,  Jeong Tae KIM

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.

Abstract translation: 描述了具有包括CrxBy的扩散阻挡层的半导体器件的金属线及其形成方法。 半导体器件的金属线包括形成在半导体衬底上的绝缘层。 绝缘层形成有金属线形成区域。 随后在金属线形成区域和绝缘层的表面上形成包括Cr x B y层的扩散阻挡层。 最后形成金属线以填充包含CrxBy层的扩散阻挡层上的绝缘层的金属线形成区域。