公开(公告)号：US20200026514A1

公开(公告)日：2020-01-23

申请号：US16526147

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308450A1

公开(公告)日：2018-10-25

申请号：US15493606

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Eric J. Hoekstra ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Eric G. Liskay ,  Joydeep Ray ,  Michael J. Norris ,  Wenyin Fu ,  Altug Koker

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G2340/06 ,  G09G2350/00

Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US11263720B2

公开(公告)日：2022-03-01

申请号：US16985329

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US20210349715A1

公开(公告)日：2021-11-11

申请号：US17319056

申请日：2021-05-12

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F9/30 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36 ,  G06F9/38

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210035257A1

公开(公告)日：2021-02-04

申请号：US16985329

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US10579121B2

公开(公告)日：2020-03-03

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F15/16 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190304049A1

公开(公告)日：2019-10-03

申请号：US16290706

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Subramaniam M. Maiyuran ,  Eric J. Hoekstra ,  Prasoonkumar Surti ,  Balaji Vembu ,  Altug Koker

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/48

Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.

公开(公告)号：US10269088B2

公开(公告)日：2019-04-23

申请号：US15493352

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Subramaniam M. Maiyuran ,  Eric J. Hoekstra ,  Prasoonkumar Surti ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/48

Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.

公开(公告)号：US20180293695A1

公开(公告)日：2018-10-11

申请号：US15483236

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.