公开(公告)号：US20220113783A1

公开(公告)日：2022-04-14

申请号：US17411878

申请日：2021-08-25

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/3209 ,  H04W52/02 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220005145A1

公开(公告)日：2022-01-06

申请号：US17375256

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Wenyin Fu ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Altug Koker ,  Nikos Kaburlasos ,  Kamal Sinha

IPC: G06T1/20 ,  G06F12/0897 ,  G06T1/60 ,  G06F9/50

Abstract: By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.

公开(公告)号：US11175719B2

公开(公告)日：2021-11-16

申请号：US16595543

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G06F1/3234 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3296 ,  G09G5/36

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US11106264B2

公开(公告)日：2021-08-31

申请号：US16805480

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06T1/20 ,  G06F1/3209 ,  H04W52/02 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04M1/72448

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200349091A1

公开(公告)日：2020-11-05

申请号：US16881271

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Prasoonkumar Surti ,  Balaji Vembu ,  Wenyin Fu ,  Bhushan M. Borole ,  Kamal Sinha

IPC: G06F12/128 ,  G06F12/0811 ,  G06F13/40 ,  G06F12/12 ,  G06T1/60 ,  G06F12/0897 ,  G06F12/084

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

公开(公告)号：US10754809B2

公开(公告)日：2020-08-25

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G11C17/18 ,  G11C17/16 ,  G11C11/4094 ,  G06F9/30 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US10748238B2

公开(公告)日：2020-08-18

申请号：US16279270

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US20200210238A1

公开(公告)日：2020-07-02

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/48 ,  G06F1/329

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US10691617B2

公开(公告)日：2020-06-23

申请号：US16113174

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  James A. Valerio ,  Altug Koker ,  Prasoonkumar P. Surti ,  Balaji Vembu ,  Wenyin Fu ,  Bhushan M. Borole ,  Kamal Sinha

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0811 ,  G06F13/40 ,  G06T1/60 ,  G06F12/0897 ,  G06F12/084

Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

公开(公告)号：US20190213161A1

公开(公告)日：2019-07-11

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G06F9/30 ,  G11C17/18 ,  G11C11/4094 ,  G11C17/16

CPC classification number: G06F13/4068 ,  G06F9/30105 ,  G06F9/30141 ,  G06F13/4077 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.