公开(公告)号：US20220198017A1

公开(公告)日：2022-06-23

申请号：US17483207

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Siyuan FU ,  Murugasamy K. NACHIMUTHU ,  Suryakanth SEKAR ,  Wei XU ,  Ruixia LI ,  Chuan SONG

IPC: G06F21/57 ,  G06F8/656

Abstract: Systems and methods to support system management mode (SMM) update and telemetry in runtime for bare metal deployments. During runtime operation of a host operating system on a bare metal platform having a management controller and including a processing unit on which the host operating system (OS) and host BIOS are executed, an out-of-band runtime update is performed to update secure execution mode (e.g., SMM) runtime firmware for the bare metal platform using an out-of-band channel comprising an interrupt driven, shared memory-based data exchange channel between the management controller and the host BIOS. This enables secure execution mode runtime firmware to be updated without during runtime without having to reboot the platform or restart the OS kernel. The out-of-band channel also supports exchange of telemetry data logged by the host BIOS during the runtime update with the management controller.

公开(公告)号：US20200257521A1

公开(公告)日：2020-08-13

申请号：US16790488

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Sarathy JAYAKUMAR ,  Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Michael A. ROTHMAN

IPC: G06F8/656 ,  G06F9/4401 ,  G06F21/57

Abstract: Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

公开(公告)号：US20190042089A1

公开(公告)日：2019-02-07

申请号：US15910933

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Anjaneya R. CHAGAM REDDY ,  Mohan J. KUMAR ,  Sujoy SEN ,  Murugasamy K. NACHIMUTHU ,  Gamil CAIN

IPC: G06F3/06

Abstract: Examples include techniques for determining a storage policy for storing data in a computing system having one or more storage nodes, each storage node including one or more storage devices. One technique includes getting rating information from a storage device of a storage node; assigning the storage device to a storage pool based at least in part on the rating information; and automatically determining a storage policy for the computing system based at least in part on the assigned storage pool and the rating information.

公开(公告)号：US20180095890A1

公开(公告)日：2018-04-05

申请号：US15283065

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Dimitrios ZIAKAS

IPC: G06F12/10 ,  G06F12/06

CPC classification number: G06F12/10 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0653 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/217

Abstract: Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which the target node is coupled. The initiator node accesses the memory coupled to the target node, by using the memory address map of the initiator node.

公开(公告)号：US20180032414A1

公开(公告)日：2018-02-01

申请号：US15728414

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  George VERGIS

IPC: G06F11/20 ,  G06F11/30 ,  G06F3/06 ,  G06F11/00

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.