公开(公告)号：US20210110067A1

公开(公告)日：2021-04-15

申请号：US17132387

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Raghavan Kumar ,  Sanu Mathew

IPC: G06F21/75 ,  G06F21/79 ,  G06F21/31

Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

公开(公告)号：US10917251B2

公开(公告)日：2021-02-09

申请号：US15942181

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/00 ,  G06F7/58

Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

公开(公告)号：US20200312404A1

公开(公告)日：2020-10-01

申请号：US16417538

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

IPC: G11C11/419 ,  H04L9/32

Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

公开(公告)号：US20200104101A1

公开(公告)日：2020-04-02

申请号：US16143770

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Sanu Mathew ,  Vikram Suresh ,  Raghavan Kumar

IPC: G06F7/58 ,  G06F21/75 ,  H04L9/32

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.

公开(公告)号：US20190305970A1

公开(公告)日：2019-10-03

申请号：US15942181

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/32 ,  H04L9/00

Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

公开(公告)号：US10346343B2

公开(公告)日：2019-07-09

申请号：US15192739

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew ,  Neeraj Upasani

IPC: H04L9/00 ,  G06F13/42 ,  G06F21/44 ,  G06F12/1009 ,  G06F12/14 ,  G06F13/16 ,  G06F21/57 ,  G06F21/76 ,  G06F21/79 ,  G09C1/00 ,  H04L9/32 ,  H04L9/06

Abstract: Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.

公开(公告)号：US10218497B2

公开(公告)日：2019-02-26

申请号：US15252741

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

IPC: G06F9/30 ,  G09C1/00 ,  H04L9/06

Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.

公开(公告)号：US11917053B2

公开(公告)日：2024-02-27

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F7/503 ,  G06F9/3012 ,  H04L9/3247

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11750402B2

公开(公告)日：2023-09-05

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F9/3877 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11695542B2

公开(公告)日：2023-07-04

申请号：US16288536

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/06 ,  H04L9/00

CPC classification number: H04L9/0637 ,  H04L9/003 ,  H04L9/065 ,  H04L9/0631 ,  H04L9/0662 ,  H04L2209/043

Abstract: An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.