公开(公告)号：US11341311B1

公开(公告)日：2022-05-24

申请号：US17356709

申请日：2021-06-24

Applicant: International Business Machines Corporation

Inventor： Joseph Koone ,  Smitha Reddy ,  Gustavo Enrique Tellez ,  Michael Alexander Bowen ,  Adam P. Matheny

IPC: G06F30/398 ,  G06F30/394 ,  G06T17/20 ,  G06F30/23 ,  G06F119/12

Abstract: Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.

公开(公告)号：US10331840B2

公开(公告)日：2019-06-25

申请号：US14996402

申请日：2016-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alice H. Lee ,  Adam P. Matheny ,  Jose Luis Pontes Neves

IPC: G06F17/50

Abstract: Methods are disclosed to determine if wiring resources are available in the neighborhood of a physically routed net in all three dimensions. Such a method can select a wire trait based on an amount of usage of each wire segment in the net and the total percentage usage of the net. The method can also re-route a net using new wiring resources after determining that wiring resources are available. The new resources can provide improved RC (delay) characteristics and reduced signal coupling. The method can be applied to a VLSI design with multiple fails.

公开(公告)号：US09928322B2

公开(公告)日：2018-03-27

申请号：US15135595

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Christopher J. Berry ,  Chris A. Cavitt ,  Adam P. Matheny ,  Jose L. Neves ,  Jesse P. Surprise ,  Michael H. Wood

IPC: G06F17/50 ,  G06F11/00

CPC classification number: G06F17/5031 ,  G06F11/00 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/68 ,  G06F2217/84

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

公开(公告)号：US09858383B2

公开(公告)日：2018-01-02

申请号：US14973893

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Kerim Kalafala ,  Tsz-Mei Ko ,  Ravichander Ledalla ,  Alice H. Lee ,  Adam P. Matheny ,  Jose L. Neves ,  Gregory M. Schaeffer

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/78 ,  G06F2217/82 ,  G06F2217/84

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

公开(公告)号：US09256705B2

公开(公告)日：2016-02-09

申请号：US14090488

申请日：2013-11-26

Applicant: International Business Machines Corporation

Inventor： Paul D. Kartschoke ,  Adam P. Matheny ,  Jose L. Neves

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F17/5036

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.