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    PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE
    1.
    发明申请
    PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE 审中-公开

    公开(公告)号：US20180082009A1

    公开(公告)日：2018-03-22

    申请号：US15832249

    申请日：2017-12-05

    Applicant: International Business Machines Corporation

    Inventor： Robert J. Allen ,  Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/82

    Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

    REDUCING REPEATER POWER
    4.
    发明申请
    REDUCING REPEATER POWER 有权
    降低重复功率

    公开(公告)号：US20140088948A1

    公开(公告)日：2014-03-27

    申请号：US14090488

    申请日：2013-11-26

    Applicant: International Business Machines Corporation

    Inventor： Paul D. Kartschoke ,  Adam P. Matheny ,  Jose L. Neves

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F17/5036

    Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

    Abstract translation: 提供了用于减少中继器功率和串扰的方法，系统和计算机可读介质。 该方法包括生成包括连接在至少一个源和至少一个宿之间的多个原始中继器的电路的模型，对多个原始中继器执行功率优化分析以将多个原始中继器改变为低功率中继器 基于预定的优化参数，对包括低功率中继器的电路的模型执行串扰分析，以确定是否存在串扰定时违反，以及当至少一个低功率中继器改变为较高功率中继器时 确定存在串扰冲突，并且当确定不存在串扰冲突时，将低功率中继器留在电路模型中。

    CROSS-HIERARCHY ANTENNA CONDITION VERIFICATION
    5.
    发明申请
    CROSS-HIERARCHY ANTENNA CONDITION VERIFICATION 有权

    公开(公告)号：US20230051392A1

    公开(公告)日：2023-02-16

    申请号：US17402710

    申请日：2021-08-16

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael Alexander Bowen ,  Gerald L Strevig, III ,  Amanda Christine Venton ,  Robert Mahlon Averill, III ,  Adam P. Matheny ,  David Wolpert ,  Mitchell R. DeHond

    IPC: G06F30/398

    Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

    METHODS AND COMPUTER PROGRAM PRODUCTS FOR VIA CAPACITANCE EXTRACTION
    7.
    发明申请
    METHODS AND COMPUTER PROGRAM PRODUCTS FOR VIA CAPACITANCE EXTRACTION 审中-公开

    公开(公告)号：US20170169151A1

    公开(公告)日：2017-06-15

    申请号：US14964863

    申请日：2015-12-10

    Applicant: International Business Machines Corporation

    Inventor： Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/82

    Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively. Unioning operation includes: unioning shapes from Cshapes collection into a non-overlapping Ctiles collection, unioning shapes from CshapesVia collection into a non-overlapping CtileVia collection, computing the tile intersections of Cshapes collection and CshapesVia collection, and removing intersections from CshapesVia collection.

    Cross-hierarchy antenna condition verification
    9.
    发明授权
    Cross-hierarchy antenna condition verification 有权

    公开(公告)号：US11941340B2

    公开(公告)日：2024-03-26

    申请号：US17402710

    申请日：2021-08-16

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael Alexander Bowen ,  Gerald L Strevig, III ,  Amanda Christine Venton ,  Robert Mahlon Averill, III ,  Adam P. Matheny ,  David Wolpert ,  Mitchell R. DeHond

    IPC: G06F30/39 ,  G06F30/398

    CPC classification number: G06F30/398

    Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

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