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公开(公告)号:US11100229B2
公开(公告)日:2021-08-24
申请号:US16515633
申请日:2019-07-18
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Veit Kleeberger , Berndt Gammel
Abstract: A hybrid device includes a plurality of diverse subsystems, including a first and a second subsystem. The first subsystem includes at least one first secured storage device configured to store a first software and a first CPU configured to boot and execute the first software. The second subsystem includes at least one second secured storage device configured to store a second software and a second CPU configured to boot and execute the second software. The first CPU is configured to generate the first hash of the first software and transmit the generated first hash of the first software to the second subsystem. The second CPU is configured to perform a first authenticity validation check on the first software using the received first hash of the first software, and generate an error signal on a condition that the first authenticity validation check on the first software fails.
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公开(公告)号:US10970399B2
公开(公告)日:2021-04-06
申请号:US16161440
申请日:2018-10-16
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Viola Rieger
Abstract: A method for processing data in a plurality of processing acts includes: configuring a plurality of processing circuits in a first configuration, in such a way that both a first and a second of the plurality of processing circuits execute a first of the plurality of processing acts; and configuring the plurality of processing circuits in a second configuration, in such a way that the first processing circuit executes a second processing act and the second processing circuit executes a third processing act, which is different than the second processing act. An apparatus is designed for carrying out the method.
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公开(公告)号:US10862670B2
公开(公告)日:2020-12-08
申请号:US15983594
申请日:2018-05-18
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Patrick Kresmer
Abstract: A system may include a plurality of matching block cipher devices, and a hardware state machine communicatively coupled to each of the plurality of matching block cipher devices. Each of the plurality of matching block cipher devices can be independently invoked by the hardware state machine such that the hardware state machine causes two or more of the plurality of matching block cipher devices to selectively perform a block-cipher-based symmetric cryptographic operation in a redundant mode or a parallel mode. The block-cipher-based symmetric cryptographic operation may be associated with securing a communication channel of an automotive system.
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公开(公告)号:US20190334720A1
公开(公告)日:2019-10-31
申请号:US16395783
申请日:2019-04-26
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Vivin Richards Allimuthu Elavarasu , Eric Pihet
Abstract: A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.
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公开(公告)号:US20250158808A1
公开(公告)日:2025-05-15
申请号:US18508443
申请日:2023-11-14
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Kenneth William Tindell
Abstract: The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message.
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26.
公开(公告)号:US20250080325A1
公开(公告)日:2025-03-06
申请号:US18459695
申请日:2023-09-01
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Gasper Skvarc Bozic
Abstract: The described techniques address issues associated with current implementations of debugging and tracing tools, which transmit trace data from tracing processes in an unencrypted form. The techniques include providing a secure means by which to convey the trace data instances outside of a monitored system utilizing an encryption scheme that leverages a number used only once (nonce) value for the encryption of the trace data instances. Advantageously, a time stamp value identified with one or more of the trace messages may be used to generate the nonce value to facilitate the encryption of the trace data instances.
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公开(公告)号:US11945451B2
公开(公告)日:2024-04-02
申请号:US16509639
申请日:2019-07-12
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Harald Zweck
CPC classification number: B60W50/0205 , B60W50/04 , B60G2800/80 , B60W2050/021 , B60W2510/18
Abstract: An electronic anomaly detection unit for use in a vehicle includes an input component for capturing an input variable, wherein the input variable contains state information for at least one component of the vehicle, a memory component for storing state values based on the input variable, a selection component for selecting selected state values from the stored state values, an association component for associating the selected state values with predefined values, wherein the predefined values define a normal state of the component of the vehicle, and a decision component for deciding whether there is an anomalous behavior in the at least one component of the vehicle, based on the association, wherein one or more of the input component, the memory component, the selection component, the association component and the decision component are implemented in hardware.
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公开(公告)号:US11849024B2
公开(公告)日:2023-12-19
申请号:US17872253
申请日:2022-07-25
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Laurent Heidt , Stefan Koeck
CPC classification number: H04L9/0643 , H04L9/0866 , H04L9/0877 , H04L9/3252
Abstract: A device is suggested for processing input data including a hardware accelerator generating a first hash value based on a first portion of the input data and a second hash value based on a second portion of the input data, wherein the first hash value is generated based on a first configuration of the hardware accelerator and wherein the second hash value is generated based on a second configuration of the hardware accelerator. Also, a method for operating such device is provided.
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公开(公告)号:US11816201B2
公开(公告)日:2023-11-14
申请号:US17661590
申请日:2022-05-02
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Harald Zweck
CPC classification number: G06F21/44 , G06F21/602 , H04L9/14
Abstract: The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.
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公开(公告)号:US11722293B2
公开(公告)日:2023-08-08
申请号:US17684670
申请日:2022-03-02
Applicant: Infineon Technologies AG
Inventor: Alexander Zeh , Marcus Janke
CPC classification number: H04L9/0643 , H04L9/0662 , H04L63/205 , H04L2209/84
Abstract: A sender device includes: a first sequence generator configured to generate a first sequence of bits having a bit pattern that incudes first bit values and second bit values; a first parsing processor configured to receive a first plurality of data blocks and the first sequence of bits, and select a first subset of data blocks and a second subset of data blocks from the first plurality of data blocks based on the bit pattern; an encryption processor configured to encrypt the selected first subset of data blocks received from the first parsing processor to generate encrypted data blocks and output the encrypted data blocks to an output terminal that is configured to output the encrypted data blocks and the selected second subset of data blocks as unencrypted data blocks from the sender device.
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