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公开(公告)号：US11374758B2
公开(公告)日：2022-06-28
申请号：US16395783
申请日：2019-04-26
Applicant: Infineon Technologies AG
Inventor： Alexander Zeh , Vivin Richards Allimuthu Elavarasu , Eric Pihet
Abstract: A transceiver is disclosed including a transmitter designed to output a first signal according to a physical communication protocol, and to output a second signal comprising at least one cryptographic datum. The first and the second signal may be overlaid onto one another as an overlay signal at the output of the transceiver, and may comply with the physical communication protocol. The overlay signal may be received and processed by a receiver.
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公开(公告)号：US20220123958A1
公开(公告)日：2022-04-21
申请号：US17468327
申请日：2021-09-07
Applicant: Infineon Technologies AG
Inventor： Jens Repp , Thorsten Hinderer , Maximilian Mangst , Eric Pihet
IPC: H04L12/40 , H03K17/687 , H03K5/01
Abstract: A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.
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公开(公告)号：US20250016027A1
公开(公告)日：2025-01-09
申请号：US18744052
申请日：2024-06-14
Applicant: Infineon Technologies AG
Inventor： Dieter Metzner , Eric Pihet , Stefan Vögele
IPC: H04L12/40
Abstract: The present application relates to a method for generating a bus transmission signal, which transitions between a dominant state, a suppressive state and a recessive state, and a corresponding circuit. The method comprises receiving a transmission control signal, which transitions between the dominant state and the recessive state, detecting a first state transition of the transmission control signal which is one of a dominant-to-recessive state transition and a recessive-to-dominant state transition and consecutively generating a plurality of transmitter control signals based on the transmission control signal, the first state transition and a plurality of delays and controlling a transmitter to transmit the bus transmission signal based on the plurality of transmitter control signals. The plurality of delays has a sequence tuple comprising a dominant-to-recessive sequence and a recessive-to-dominant sequence and a suppressive delay only included in the dominant-to-recessive sequence, causing the bus transmission signal to remain in the suppressive state.
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公开(公告)号：US10728064B2
公开(公告)日：2020-07-28
申请号：US16296042
申请日：2019-03-07
Applicant: Infineon Technologies AG
Inventor： Maximilian Mangst , Eric Pihet , Thorsten Hinderer
IPC: H04L25/49 , H04L7/04 , H04L25/02 , H04L25/493
Abstract: A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.
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公开(公告)号：US10592456B2
公开(公告)日：2020-03-17
申请号：US16052371
申请日：2018-08-01
Applicant: Infineon Technologies AG
Inventor： Thorsten Hinderer , David Astrom , Eric Pihet
IPC: G06F13/20 , G06F13/40 , G06F1/26 , G06F1/3296 , G06F13/42
Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.
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Patent Agency Ranking
公开(公告)号：US20190288886A1
公开(公告)日：2019-09-19
申请号：US16296042
申请日：2019-03-07
Applicant: Infineon Technologies AG
Inventor： Maximilian Mangst , Eric Pihet , Thorsten Hinderer
Abstract: A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.
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公开(公告)号：US10042807B2
公开(公告)日：2018-08-07
申请号：US15091337
申请日：2016-04-05
Applicant: Infineon Technologies AG
Inventor： Thorsten Hinderer , David Astrom , Eric Pihet
Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.
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公开(公告)号：US09965426B2
公开(公告)日：2018-05-08
申请号：US14591745
申请日：2015-01-07
Applicant: Infineon Technologies AG
Inventor： Eric Pihet
CPC classification number: G06F13/4027 , G05F1/625 , G06F13/4221
Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.
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公开(公告)号：US20160196230A1
公开(公告)日：2016-07-07
申请号：US14591745
申请日：2015-01-07
Applicant: Infineon Technologies AG
Inventor： Eric Pihet
CPC classification number: G06F13/4027 , G05F1/625 , G06F13/4221
Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.
Abstract translation: 根据各种实施例，一种操作双线数字总线的方法包括在第一接口节点向双线数字总线施加偏置电压，测量第一接口节点处的双线数字总线的共模电压 并且基于所测量的共模电压来调整第一接口节点处的偏置电压。
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公开(公告)号：US20240332954A1
公开(公告)日：2024-10-03
申请号：US18191528
申请日：2023-03-28
Applicant: Infineon Technologies AG
Inventor： Christian Cornelius Russ , Gabriel-Dumitru Cretu , Filippo Magrini , Bernhard Stein , Eric Pihet
Abstract: An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.
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