公开(公告)号：US11722293B2

公开(公告)日：2023-08-08

申请号：US17684670

申请日：2022-03-02

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Marcus Janke

IPC: H04L9/06 ,  H04L9/40

CPC classification number: H04L9/0643 ,  H04L9/0662 ,  H04L63/205 ,  H04L2209/84

Abstract: A sender device includes: a first sequence generator configured to generate a first sequence of bits having a bit pattern that incudes first bit values and second bit values; a first parsing processor configured to receive a first plurality of data blocks and the first sequence of bits, and select a first subset of data blocks and a second subset of data blocks from the first plurality of data blocks based on the bit pattern; an encryption processor configured to encrypt the selected first subset of data blocks received from the first parsing processor to generate encrypted data blocks and output the encrypted data blocks to an output terminal that is configured to output the encrypted data blocks and the selected second subset of data blocks as unencrypted data blocks from the sender device.

公开(公告)号：US20230367912A1

公开(公告)日：2023-11-16

申请号：US18311981

申请日：2023-05-04

Applicant: Infineon Technologies AG

Inventor： Marcus Janke ,  Steffen Sonnekalb

IPC: G06F21/64 ,  G06F21/79

CPC classification number: G06F21/64 ,  G06F21/79

Abstract: A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.

公开(公告)号：US20240428037A1

公开(公告)日：2024-12-26

申请号：US18749696

申请日：2024-06-21

Applicant: Infineon Technologies AG

Inventor： Walther Pachler ,  Matthias Seiß ,  Christian Goral ,  Marcus Janke

IPC: G06K19/073 ,  G06K19/07 ,  G06K19/077

Abstract: A carrier structure including a carrier, an antenna structure on the carrier and a reception region designed for removable reception of an RF chip. The reception region is arranged relative to the antenna structure in such a way that inductive coupling to the antenna structure is enabled when the RF chip is arranged in the reception region. An inductive blocking element on the carrier blocks communication with the RF chip using the antenna structure in a first position of the inductive blocking element. In a second position of the inductive blocking element, the inductive blocking element enables communication with the RF chip using the antenna structure.

公开(公告)号：US09471793B2

公开(公告)日：2016-10-18

申请号：US14137065

申请日：2013-12-20

Applicant: Infineon Technologies AG

Inventor： Markus Gail ,  Gerd Dirscherl ,  Marcus Janke

IPC: G06F7/04 ,  G06F21/60 ,  G06F21/00 ,  G06F21/71

CPC classification number: G06F21/60 ,  G06F21/00 ,  G06F21/71 ,  G06F2221/2121

Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.

Abstract translation: 嵌入式安全模块包括安全处理器，易失性和非易失性存储器以及接口。 安全处理器包括形成在半导体管芯的一个或多个半导体层中的晶体管，并且对由安全处理器访问的数据和/或代码实现一个或多个与安全相关的功能。 易失性存储器被制造在与安全处理器相同的半导体管芯上，并存储由安全处理器访问的数据和/或代码。 非易失性存储器包括设置在半导体芯片的每个半导体层之上的非易失性存储单元，并且安全地存储由安全处理器访问的数据和/或代码中的至少一个以及与数据和/或代码相关的安全信息 由安全处理器访问。 该接口在与安全处理器相同的半导体管芯上制造，并为安全处理器提供通信接口。

公开(公告)号：US20150278670A1

公开(公告)日：2015-10-01

申请号：US14673901

申请日：2015-03-31

Applicant: Infineon Technologies AG

Inventor： Peter Laackmann ,  Marcus Janke

IPC: G06K19/06

CPC classification number: G06K19/06206

Abstract: In various embodiments, a chip card is provided. The chip card includes a chip having a memory unit and a control unit, and a coil which is electrically coupled to the control unit and is intended to generate a magnetic field. The control unit and the coil may be set up to simulate a magnetic strip using the generated magnetic field.

Abstract translation: 在各种实施例中，提供了芯片卡。 芯片卡包括具有存储单元和控制单元的芯片，以及与该控制单元电耦合并用于产生磁场的线圈。 控制单元和线圈可以被设置成使用所产生的磁场来模拟磁条。

公开(公告)号：US20140223569A1

公开(公告)日：2014-08-07

申请号：US14137065

申请日：2013-12-20

Applicant: Infineon Technologies AG

Inventor： Markus Gail ,  Gerd Dirscherl ,  Marcus Janke

IPC: G06F21/60

CPC classification number: G06F21/60 ,  G06F21/00 ,  G06F21/71 ,  G06F2221/2121

Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.

Abstract translation: 嵌入式安全模块包括安全处理器，易失性和非易失性存储器以及接口。 安全处理器包括形成在半导体管芯的一个或多个半导体层中的晶体管，并且对由安全处理器访问的数据和/或代码实现一个或多个与安全相关的功能。 易失性存储器被制造在与安全处理器相同的半导体管芯上，并存储由安全处理器访问的数据和/或代码。 非易失性存储器包括设置在半导体芯片的每个半导体层之上的非易失性存储单元，并且安全地存储由安全处理器访问的数据和/或代码中的至少一个以及与数据和/或代码相关的安全信息 由安全处理器访问。 该接口在与安全处理器相同的半导体管芯上制造，并为安全处理器提供通信接口。

公开(公告)号：US20230114775A1

公开(公告)日：2023-04-13

申请号：US17958859

申请日：2022-10-03

Applicant: Infineon Technologies AG

Inventor： Marcus Janke ,  Manfred Roth ,  Stephan Miculcy

IPC: G06F21/57 ,  G06F8/65 ,  H04L9/08 ,  H04L9/32

Abstract: A portable chip device comprises a chip having an operating system and a loader, the loader being configured to load a software module onto the chip and/or to render the software module in the chip executable, a communications interface configured to communicate with an external reader, the portable chip device being configured to carry out a software module update by: receiving a second key in the loader via communication between the external reader and the communications interface, where the communication is encrypted with a first key, and storing the second key in the loader, the operating system being configured to provide the decryption of the communication encrypted with the first key, authenticating the external reader using the symmetric key stored in the loader, receiving software module update data in the loader via the communications interface, and executing the software module update with the software module update data.

公开(公告)号：US11177953B2

公开(公告)日：2021-11-16

申请号：US16561311

申请日：2019-09-05

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Martin Brunner ,  Marcus Janke

IPC: H04L29/06 ,  H04L9/08 ,  H04L9/32 ,  G06F21/57

Abstract: An authentication system includes a microcontroller having a unique identifier (ID) and a first key pair including a microcontroller secret key and a microcontroller public key. The microcontroller is configured to store the unique ID, the first key pair, a digital signature of the unique ID, the digital signature being generated using an external secret key of a second key pair, and a digital certificate of the microcontroller public key that is signed by the external secret key of the second key pair. The second key pair includes the external secret key and an external public key. The authentication system further includes a controller configured to perform a first authenticity validation check on the unique ID using the external public key and perform a second authenticity validation check on the microcontroller public key using the external public key.

公开(公告)号：US20180212781A1

公开(公告)日：2018-07-26

申请号：US15416987

申请日：2017-01-26

Applicant: Infineon Technologies AG

Inventor： Goran Keser ,  Phillip Gesien ,  Guenter Hofer ,  Marcus Janke

IPC: H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3247 ,  H04L9/3236 ,  H04L63/0435 ,  H04L63/123 ,  H04W4/48

Abstract: An intermediate servant device connected in a daisy chain configuration with a set of devices is described. The intermediate servant device may be configured to receive, from a previous servant device of the set of servant devices, a request for data, a first response to the request for data, and authentication information for the first response to the request for data. The intermediate servant device may be further configured to generate a second response to the request for data and determine authentication information for the second response based on the authentication information for the first response, the second response, and a key assigned to the intermediate servant device. The intermediate servant device may be further configured to output at least the authentication information for the second response, the first response, and the second response.

公开(公告)号：US09279856B2

公开(公告)日：2016-03-08

申请号：US13656761

申请日：2012-10-22

Applicant: Infineon Technologies AG

Inventor： Peter Laackmann ,  Marcus Janke

IPC: G01R31/3187 ,  H01L21/50 ,  H01L23/544 ,  G01R31/317

CPC classification number: G01R31/31719 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, a die is provided. The die may include a physical unclonable function circuit configured to provide an output signal, wherein the output signal is dependent on at least one physical characteristic specific to the die; and a self-test circuit integrated with the physical unclonable function circuit on the die, wherein the self-test circuit is configured to provide at least one test input signal to the physical unclonable function circuit and to determine as to whether the output signal provided in response to the at least one test input signal fulfills a predefined criterion.

Abstract translation: 在各种实施例中，提供了一个模具。 芯片可以包括被配置为提供输出信号的物理不可克隆功能电路，其中输出信号取决于芯片特有的至少一个物理特性; 以及与所述管芯上的所述物理不可克隆功能电路集成的自检电路，其中所述自检电路被配置为向所述物理不可克隆功能电路提供至少一个测试输入信号，并且确定所提供的输出信号是否 对至少一个测试输入信号的响应满足预定义的标准。