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公开(公告)号：US09276580B2
公开(公告)日：2016-03-01
申请号：US14660474
申请日：2015-03-17
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/096
摘要： A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.
摘要翻译： 动态逻辑电路包括：预充电装置，其被配置为根据第一和第二评估时钟信号对动态节点进行预充电。 第一评估树被配置为响应于根据第一评估时钟信号的一个或多个第一输入信号来将动态节点评估为第一值。 第二评估树，其被配置为响应于根据第二评估时钟信号的一个或多个第二输入信号将动态节点评估为第二值。
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公开(公告)号：US20200243120A1
公开(公告)日：2020-07-30
申请号：US16257562
申请日：2019-01-25
发明人： Yutaka Nakamura
IPC分类号： G11C7/06 , G11C5/14 , G11C11/4091
摘要： A two-stage gated-diode sense amplifier includes a first transistor connected to an input node, a second transistor connected to a boost node, the input node and a setting line, a first inverter including a third transistor connected to a power supply voltage (VDD), a first output corresponding to the first inverter and the setting line, and a fourth transistor connected to ground, the first output and the setting line, a fifth transistor connected to the first output, the first transistor and the boost node, and a second associated with a second output corresponding to the second inverter, the second inverter including a sixth transistor connected to VDD, the second output and the first output, and a seventh transistor connected to ground, the second output and the first output.
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公开(公告)号：US20200227110A1
公开(公告)日：2020-07-16
申请号：US16248886
申请日：2019-01-16
发明人： Yutaka Nakamura
IPC分类号： G11C11/4091
摘要： A sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.
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公开(公告)号：US20170185891A1
公开(公告)日：2017-06-29
申请号：US14980295
申请日：2015-12-28
摘要： A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.
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公开(公告)号：US20170141568A1
公开(公告)日：2017-05-18
申请号：US15417656
申请日：2017-01-27
发明人： Chen Guo , Yutaka Nakamura , Jun Sawada
CPC分类号： H02H9/046 , H01L27/0266 , H01L27/088 , H03K3/353
摘要： An embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output.
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公开(公告)号：US09030234B2
公开(公告)日：2015-05-12
申请号：US13937396
申请日：2013-07-09
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/096
摘要： A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.
摘要翻译： 有限开关动态逻辑（LSDL）电路包括动态逻辑电路和静态逻辑电路。 动态逻辑电路包括预充电装置，其被配置为在第一评估时钟信号和第二评估时钟信号的预充电阶段期间预充电动态节点。 第一评估树被配置为在第一评估时钟信号的评估阶段期间响应于一个或多个第一输入信号来评估动态节点为第一逻辑值。 第二评估树被配置为在第二评估时钟信号的评估阶段期间响应于一个或多个第二输入信号将动态节点评估为第二逻辑值。 静态逻辑电路被配置为根据输出锁存时钟信号响应于动态节点提供LSDL电路的输出。
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公开(公告)号：US20130328593A1
公开(公告)日：2013-12-12
申请号：US13937396
申请日：2013-07-09
发明人： Leland Chang , Robert K. Montoye , Yutaka Nakamura
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/096
摘要： A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.
摘要翻译： 有限开关动态逻辑（LSDL）电路包括动态逻辑电路和静态逻辑电路。 动态逻辑电路包括预充电装置，其被配置为在第一评估时钟信号和第二评估时钟信号的预充电阶段期间预充电动态节点。 第一评估树被配置为在第一评估时钟信号的评估阶段期间响应于一个或多个第一输入信号来评估动态节点为第一逻辑值。 第二评估树被配置为在第二评估时钟信号的评估阶段期间响应于一个或多个第二输入信号将动态节点评估为第二逻辑值。 静态逻辑电路被配置为根据输出锁存时钟信号响应于动态节点提供LSDL电路的输出。
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公开(公告)号：US11687148B1
公开(公告)日：2023-06-27
申请号：US17729638
申请日：2022-04-26
发明人： Robert K. Montoye , Kevin Tien , Yutaka Nakamura , Jeffrey Haskell Derby , Martin Cochet , Todd Edward Takken , Xin Zhang
IPC分类号： G06F1/00 , G06F1/3296 , G06F1/324
CPC分类号： G06F1/3296 , G06F1/324
摘要： A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.
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公开(公告)号：US10930325B2
公开(公告)日：2021-02-23
申请号：US16257562
申请日：2019-01-25
发明人： Yutaka Nakamura
IPC分类号： G11C7/14 , G11C7/06 , G11C5/14 , G11C11/4091 , H01L29/739 , G11C11/419
摘要： A two-stage gated-diode sense amplifier includes a first transistor connected to an input node, a second transistor connected to a boost node, the input node and a setting line, a first inverter including a third transistor connected to a power supply voltage (VDD), a first output corresponding to the first inverter and the setting line, and a fourth transistor connected to ground, the first output and the setting line, a fifth transistor connected to the first output, the first transistor and the boost node, and a second associated with a second output corresponding to the second inverter, the second inverter including a sixth transistor connected to VDD, the second output and the first output, and a seventh transistor connected to ground, the second output and the first output.
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公开(公告)号：US10755767B2
公开(公告)日：2020-08-25
申请号：US16248886
申请日：2019-01-16
发明人： Yutaka Nakamura
IPC分类号： G11C11/4074 , G11C11/4091 , G11C11/4096
摘要： A sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.
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