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34 条记录 (耗时 0.019 秒)

    Cascode complimentary dual level shifter
    1.
    发明授权
    Cascode complimentary dual level shifter 有权

    公开(公告)号：US10115450B1

    公开(公告)日：2018-10-30

    申请号：US15617020

    申请日：2017-06-08

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： John K. DeBrosse ,  Yutaka Nakamura

    IPC分类号： G11C5/14 ,  G11C11/408 ,  H03K3/356

    摘要： A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.

    SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES
    4.
    发明申请
    SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES 有权
    共享位线SMT MRAM阵列与位线之间的分束晶体管

    公开(公告)号：US20130265821A1

    公开(公告)日：2013-10-10

    申请号：US13887289

    申请日：2013-05-04

    申请人： International Business Machines Corporation ,  MagIC Technologies, Inc.

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    LUT based neuron membrane potential update scheme in STDP neuromorphic systems
    7.
    发明授权
    LUT based neuron membrane potential update scheme in STDP neuromorphic systems 有权

    公开(公告)号：US10748058B2

    公开(公告)日：2020-08-18

    申请号：US14980295

    申请日：2015-12-28

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Kohji Hosokawa ,  Masatoshi Ishii ,  Yutaka Nakamura ,  Junka Okazawa ,  Takeo Yasuda

    IPC分类号： G06N3/063 ,  G06N3/04

    摘要： A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.

    Time division multiplexed limited switch dynamic logic
    10.
    发明授权
    Time division multiplexed limited switch dynamic logic 有权
    时分复用有限开关动态逻辑

    公开(公告)号：US09281821B2

    公开(公告)日：2016-03-08

    申请号：US14665942

    申请日：2015-03-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Leland Chang ,  Robert K. Montoye ,  Yutaka Nakamura

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963 ,  H03K19/096

    摘要： A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

    摘要翻译： 一种用于在有限开关动态逻辑电路中实现双重泵浦的方法包括根据第一时钟信号和第二时钟信号对动态节点进行预充电。 根据第一时钟信号，动态节点响应于第一评估树的一个或多个第一输入信号而被评估为第一值。 响应于根据第二时钟信号的第二评估树的一个或多个第二输入信号，动态节点被评估为第二值。