Abstract:
A peeling tap adhering method for adhering a peeling tape (4) to a surface protection film (11) adhered to the front surface of a wafer (20), comprises the steps of: supporting the wafer on a table (31) under the condition that the surface protection film is directed upward; adhering the peeling tape onto the surface protection film by pressing the peeling tape onto the surface protection film when a peeling tape adhering means (46) is lowered; detecting the pressure between the surface protection film of the wafer and the peeling tape adhering means; and stopping the peeling tape adhering means from lowering in the case where a pressure detection value (P) is not less than a predetermined value (P0). Due to the foregoing, it is possible to prevent the wafer from being cracked. Further, it is possible to prevent the peeling tape and the dicing tape from adhering to each other. When the distance (L) between the surface protection film of the wafer and the peeling tape adhering means becomes a value not more than a predetermined value (L0), the peeling tape sticking means may be stopped from lowering.
Abstract:
A tape adhering device (10) comprises: a drawing roller (42) for drawing out a tape (3); a tape fixing means (47) for fixing one portion of the tape drawn out from the drawing roller; a tape drawing means (62) for drawing out a predetermined amount of tape, which is fixed by the tape fixing means, from the drawing roller between the tape fixing means and the drawing roller; and a tape adhering means (49, 31, 37) for adhering the tape, which is located in the downstream of the tape fixing means, onto an object to be adhered (20, 36) under the condition that fixing operation of the tape by the tape fixing means is released. It is preferable that the length of the tape drawn out by the tape drawing means is not less than the diameter of the object to be adhered. Due to the foregoing, it is possible to prevent wrinkles from being form on the tape at the time of adhering the tape.
Abstract:
A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a semiconductor substrate as a mesa groove, wherein at least the second groove is covered with an electrical insulator. The upper surface of the electrical insulator is located approximately as high as or lower than the upper surface of the electrical insulating film. Thus, especially in a mesa semiconductor device with a high-voltage resistance, an insulating protective layer having a sufficient thickness can be formed stably over the entire region of a mesa groove. As a result, the variation in high-voltage resistance characteristics can be decreased and the processing yield affected by breakage or cracking in the mesa groove region during subsequent processes caused by the formation of the mesa groove can be improved greatly.