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公开(公告)号：US08854996B2
公开(公告)日：2014-10-07
申请号：US13183953
申请日：2011-07-15
IPC分类号： H04L12/801 , H04L12/741 , G06F9/38
CPC分类号： G06F9/3885 , H04L45/74 , H04L47/10
摘要： Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
摘要翻译： 为包括解析器的网络处理器提供机制，该解析器可操作以在正常操作模式或重复操作模式下工作，解析器处于正常操作模式中，分别在第一和第二工作循环中执行至少一个规则， 在重复操作模式中的解析器可操作以重复执行重复指令，执行对应于一个工作循环的每个重复。
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公开(公告)号：US07995472B2
公开(公告)日：2011-08-09
申请号：US12348938
申请日：2009-01-06
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。
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公开(公告)号：US07466715B2
公开(公告)日：2008-12-16
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译： 用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。 每个单独的数据包由FCB描述和控制。 与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。 当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。 当帧在输入队列中时，格式不需要第三个字。
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公开(公告)号：US07277982B2
公开(公告)日：2007-10-02
申请号：US10899937
申请日：2004-07-27
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
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公开(公告)号：US6104715A
公开(公告)日：2000-08-15
申请号：US974285
申请日：1997-11-19
申请人： Claude Basso , Richard H. Boivie , Jean L. Calvignac , Douglas Dykeman , Daniel Orsatti , Robert A. Sultan , Fabrice J. Verplanken
发明人： Claude Basso , Richard H. Boivie , Jean L. Calvignac , Douglas Dykeman , Daniel Orsatti , Robert A. Sultan , Fabrice J. Verplanken
CPC分类号： H04L49/3081 , H04Q11/0478 , H04L2012/5648
摘要： This invention relates to the merging of data cells arriving at an Asynchronous Transfer Mode (ATM) switching node from data frames originating with a number of senders. As is standard in ATM networks, each originating frame is segmented into a series of cells each having Virtual Path Identifier (VPI) and a Virtual Channel Identifier (VCI) in its header portion. On arrival at each switching node, the VCI of the first cell of a frame is overwritten by a new outgoing VCI value that is used for all other cells of the frame. Thus, the actual movement of each cell through the network is controlled only by the cell's VPI, whereas the VCI field is used only to distinguish frames from each other. A feature of the invention is that it can accommodate Early Packet Discard in a simple way by associated any discard indication determined for a frame with the outgoing VCI value which also applies to all cells of the entire frame.
摘要翻译： 本发明涉及到达异码传输模式（ATM）交换节点的数据单元与源自多个发送者的数据帧的合并。 如ATM网络中的标准，每个始发帧被分段成一系列小区，每个小区在其报头部分中具有虚拟路径标识符（VPI）和虚拟信道标识符（VCI）。 在到达每个交换节点时，帧的第一个单元的VCI被用于帧的所有其他单元的新的输出VCI值覆盖。 因此，通过网络的每个小区的实际移动仅由小区的VPI控制，而VCI字段仅用于将帧彼此区分开。 本发明的一个特征在于，它可以通过相关联的任何丢弃指示来适应早期分组丢弃，所述丢弃指示对于具有输出VCI值的帧也是适用于整个帧的所有小区。
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公开(公告)号：US08762399B2
公开(公告)日：2014-06-24
申请号：US13475990
申请日：2012-05-20
IPC分类号： G06F17/30
CPC分类号： G06F17/30002 , G06F17/30949 , H04L9/00 , H04L9/3236 , H04L45/7453
摘要： An improved computer system that can include a controller having a computer processor, the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller. The system may also include a collision avoidance apparatus that reduces hashing collisions by using a plurality of tables and a plurality of keys per bucket. The system may further include a hash apparatus in communication with the controller to map the plurality of keys to the plurality of tables where the hash apparatus uses a single hash logic to provide an avalanche effect when one key is changed which results in nearly half of bits changing in the plurality of tables.
摘要翻译： 一种改进的计算机系统，其可以包括具有计算机处理器的控制器，所述控制器在与引入到控制器的新组件接口时减少插入时间和/或冲突。 该系统还可以包括通过使用多个表和每个桶的多个密钥来减少散列冲突的冲突避免装置。 该系统还可以包括与控制器通信的散列装置，以将多个密钥映射到多个表，其中散列装置使用单个散列逻辑以在一个密钥改变时提供雪崩效应，这导致几乎一半的比特 改变多个表。
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公开(公告)号：US20130311436A1
公开(公告)日：2013-11-21
申请号：US13475973
申请日：2012-05-19
IPC分类号： G06F17/30
CPC分类号： G06F17/00 , G06F17/30097 , G06F17/3033
摘要： An improved computer system may include a controller including a computer processor. The system may also include a selector apparatus in communication with the controller to choose a table having a higher collision quality index than other tables under consideration by the selector apparatus. The system may further include an exchanger apparatus to configure a standby table that replaces the table chosen by the selector apparatus. The system may additionally include a switch that changes a hash function based upon the exchanger apparatus' replacement of the chosen table to enable the controller to reduce insertion times and/or collisions when interfacing with new components introduced to the controller.
摘要翻译： 改进的计算机系统可以包括包括计算机处理器的控制器。 该系统还可以包括与控制器通信的选择器装置，以选择具有比选择装置考虑的其它表格更高的冲突质量指标的表格。 该系统还可以包括交换装置，用于配置替换由选择装置选择的表的备用表。 该系统可以另外包括基于交换机设备更换所选择的表来改变散列函数的开关，以使得当与引入控制器的新组件接口时，控制器能够减少插入时间和/或冲突。
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28.发明授权Assignment constraint matrix for assigning work from multiple sources to multiple sinks 失效分配约束矩阵，用于将工作从多个源分配到多个汇点公开(公告)号：US08391305B2
公开(公告)日：2013-03-05
申请号：US12650080
申请日：2009-12-30
申请人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L49/9047
摘要： An assignment constraint matrix is used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.
摘要翻译： 分配约束矩阵用于从多个源（例如网络处理设备中的数据队列）向诸如网络处理设备中的处理器线程的多个宿分配诸如数据分组的工作。 分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。 多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。 合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。
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公开(公告)号：US20120155492A1
公开(公告)日：2012-06-21
申请号：US12974689
申请日：2010-12-21
申请人： Francois Abel , Jean L. Calvignac , Christoph Hagleitner , Jonathan B. Rohrer , Jan Van Lunteren , Fabrice J. Verplanken
发明人： Francois Abel , Jean L. Calvignac , Christoph Hagleitner , Jonathan B. Rohrer , Jan Van Lunteren , Fabrice J. Verplanken
IPC分类号： H04J3/24
CPC分类号： H04J3/1682
摘要： A data path for streaming data includes a plurality of sequential data registers, each of the plurality of sequential data registers comprising a plurality of data fields, wherein the streaming data moves sequentially through the sequential data registers; and a multiplexing unit, the multiplexing unit configured such that the multiplexing unit has access to each of the plurality of data fields of the plurality of sequential data registers, and wherein the multiplexing unit is configured to extract data from the streaming data as the streaming data moves through the sequential data registers in response to a data request.
摘要翻译： 用于流数据的数据路径包括多个顺序数据寄存器，所述多个顺序数据寄存器中的每一个包括多个数据字段，其中所述流数据顺序地通过所述顺序数据寄存器移动; 以及多路复用单元，所述复用单元被配置为使得所述复用单元能够访问所述多个顺序数据寄存器中的所述多个数据字段中的每一个，并且其中所述复用单元被配置为从所述流式数据中提取数据作为所述流数据 响应于数据请求，移动顺序数据寄存器。
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30.发明授权公开(公告)号：US07483429B2
公开(公告)日：2009-01-27
申请号：US11133477
申请日：2005-05-18
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。
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