公开(公告)号：US20050055532A1

公开(公告)日：2005-03-10

申请号：US10933266

申请日：2004-09-03

申请人： James Yu

发明人： James Yu

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0292 ,  G06F2212/7201

摘要： A method for efficiently controlling read/write of a flash memory is proposed, wherein two address mapping tables and an empty block FIFO mechanism are built. A zone address mapping table matched with its empty block FIFO data is used for the logical address of the file allocation table (FAT). When a host end performs read/write to a flash memory, no matter to which zone the zone address mapping table corresponds, it is not necessary to rebuild the FAT address mapping table. Moreover, a cache address mapping table and its empty block FIFO data can be added. When the logical address is not in the zone address mapping table and the FAT address mapping table, a smaller cache address mapping table is first built to increase the system speed, let control of the flash memory be more efficient, and distribute the utility rate of each block.

摘要翻译： 提出了一种有效控制闪速存储器的读/写的方法，其中构建了两个地址映射表和一个空块FIFO机制。 与其空块FIFO数据匹配的区域地址映射表用于文件分配表（FAT）的逻辑地址。 当主机端对闪存执行读/写操作时，无论区域地址映射表对应于哪个区域，都不需要重建FAT地址映射表。 此外，可以添加高速缓存地址映射表及其空块FIFO数据。 当逻辑地址不在区域地址映射表和FAT地址映射表中时，首先构建较小的缓存地址映射表，以提高系统速度，使闪存的控制更有效率，并分配 每个块。

公开(公告)号：US09672559B2

公开(公告)日：2017-06-06

申请号：US13523050

申请日：2012-06-14

申请人： James Yu ,  Geoffrey A. Colbath ,  Kaunish Patel ,  Brian J. Jordan, Jr.

发明人： James Yu ,  Geoffrey A. Colbath ,  Kaunish Patel ,  Brian J. Jordan, Jr.

IPC分类号： G06Q30/06 ,  G06Q30/08

CPC分类号： G06Q30/0633

摘要： A user interface for displaying retail search results is disclosed. The system and methods allow users to search for a plurality of retail items while simultaneously viewing a plurality of search results for each of the plurality of retail items. This interface allows users to easily compare the search results for each retail item, and to purchase a plurality of retail items simultaneously. In one example of the present disclosure, users may enter a plurality of retail items into a shopping list. The system may then display multiple results for each item on the shopping list in a carousel-like user interface, so users may view a plurality of results for a plurality of items simultaneously.

公开(公告)号：US20130262884A1

公开(公告)日：2013-10-03

申请号：US13456810

申请日：2012-04-26

申请人： James Yu

发明人： James Yu

IPC分类号： G06F1/26 ,  H04B3/00

CPC分类号： H04L12/40045 ,  H04L12/10 ,  H04M3/18

摘要： Low-frequency noise interference prevention in power over Ethernet (PoE) systems. A PoE device such as a power sourcing equipment (PSE) and/or a powered device (PD) is coupled to center taps of data transformers on multiple wire pairs used for high-data rate transmission via series high-impedance inductive devices.

摘要翻译： 以太网供电（PoE）系统中的低频噪声干扰预防。 诸如电源设备（PSE）和/或供电设备（PD）的PoE设备被耦合到通过串联高阻抗感应设备用于高数据速率传输的多个线对上的数据变压器的中心抽头。

公开(公告)号：US20120159239A1

公开(公告)日：2012-06-21

申请号：US13083394

申请日：2011-04-08

申请人： Peter B. Chon ,  James Yu ,  David M. Olson ,  Timothy E. Hoglund ,  Gary J. Piccirillo

发明人： Peter B. Chon ,  James Yu ,  David M. Olson ,  Timothy E. Hoglund ,  Gary J. Piccirillo

IPC分类号： G06F12/16 ,  G06F11/14

CPC分类号： G06F11/1441 ,  G06F1/30 ,  G06F11/1052

摘要： Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

摘要翻译： 公开了电力隔离和备用系统。 当检测到电源故障条件时，临时存储器被刷新到SDRAM。 在刷新之后，接口被停止，除了SDRAM子系统之外的大多数芯片的电源被去除。 SDRAM子系统将数据从SDRAM复制到闪存。 在路上，数据可以被加密，和/或计算数据完整性签名。 为了恢复数据，SDRAM子系统将数据从闪存复制到SDRAM。 一路上，正在恢复的数据可能被解密，和/或检查数据完整性签名。

公开(公告)号：US08015068B2

公开(公告)日：2011-09-06

申请号：US12539219

申请日：2009-08-11

申请人： Sanjana Swamy ,  Karen S. Holtman ,  Arnold S. Eroles ,  James Yu ,  Robert Mills ,  Daniel Levine ,  Jim Huppert ,  Daniel S. Grimm ,  Shailesh Prakash

发明人： Sanjana Swamy ,  Karen S. Holtman ,  Arnold S. Eroles ,  James Yu ,  Robert Mills ,  Daniel Levine ,  Jim Huppert ,  Daniel S. Grimm ,  Shailesh Prakash

IPC分类号： G06Q30/00

CPC分类号： G06Q10/109 ,  G06Q30/06 ,  G06Q30/0601 ,  G06Q30/0633 ,  G06Q30/0641

摘要： A system and method for allowing a user to schedule pickup of an ordered item provides a user interface having user interface elements for allowing a user to specify a frequency with which an order is it to be picked up, for informing a user as to availability of the item for pickup, and/or for allowing a user to request that an item be held in reserve for pickup within a given period of time, such as 24 hours. Frequency options provided to the user for selection when scheduling an order for pickup may include a one-time frequency, a daily frequency, a weekly frequency, a monthly frequency, and user specified dates. The information as to availability of the item for pickup is determined considering a time of order and real-time stocking information for the item.

摘要翻译： 用于允许用户调度订购物品的拾取的系统和方法提供了具有用户界面元素的用户接口，用于允许用户指定要被拾取的订单的频率，以通知用户可用性 和/或允许用户在给定的时间段（例如24小时）内请求保留物品以备用于拾取的物品。 在调度拾取订单时向用户提供的频率选项可以包括一次频率，每日频率，每周频率，每月频率和用户指定的日期。 关于拾取项目的可用性的信息是根据订单的时间和项目的实时存货信息来确定的。

公开(公告)号：US07956616B2

公开(公告)日：2011-06-07

申请号：US12749489

申请日：2010-03-29

申请人： James Yu

发明人： James Yu

IPC分类号： G01R31/08

CPC分类号： G01R27/04 ,  H04L12/10

摘要： A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

摘要翻译： 一种用于测量以太网供电（PoE）应用中的电缆电阻的系统和方法。 被动设备中的短路模块被设计成在接收到电缆电阻检测电压时产生短路效应。 电缆电阻检测电压可以被设计为大于用于检测或分类的电压，并且小于用于供电设备供电的电压。 电源设备产生短路效应时电流的测量可以计算给定PoE端口电缆的实际电阻。

公开(公告)号：US20110055598A1

公开(公告)日：2011-03-03

申请号：US12552858

申请日：2009-09-02

申请人： James Yu

发明人： James Yu

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/266 ,  H04L12/10

摘要： Embodiments of power sourcing equipment (PSE) utilizing AC disconnect are provided herein. In one embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage over a data communications medium, a controller configured to provide an AC disconnect signal over the data communications medium, and a parallel inductor-capacitor (LC) circuit coupled between the DC supply and the data communications medium. The parallel LC circuit is configured to isolate the DC supply from the AC disconnect signal. In another embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage at an output, an inductor coupled between the output of the DC supply and a data communications medium, and a capacitor coupled between the data communications medium and ground. The inductor and capacitor form a series LC circuit configured to generate an AC disconnect signal.

摘要翻译： 本文提供了使用AC断开的电源设备（PSE）的实施例。 在一个实施例中，提供了一种PSE，其包括配置成通过数据通信介质提供DC电压的DC电源，被配置为在数据通信介质上提供AC断开信号的控制器，以及并联电感器 - 电容器（LC）电路 耦合在DC电源和数据通信介质之间。 并联LC电路被配置为将DC电源与AC断开信号隔离。 在另一个实施例中，提供了一种PSE，其包括被配置为在输出处提供DC电压的DC电源，耦合在DC电源的输出和数据通信介质之间的电感器以及耦合在数据通信介质和地之间的电容器 。 电感器和电容器形成串联LC电路，其被配置为产生AC断开信号。

公开(公告)号：US20100277293A1

公开(公告)日：2010-11-04

申请号：US12433080

申请日：2009-04-30

申请人： James Yu ,  Minh Tran

发明人： James Yu ,  Minh Tran

IPC分类号： G05B11/01

CPC分类号： H04L12/10

摘要： A system and method for enabling power applications over a single conductor pair. In one embodiment, data transformers are coupled to a single conductor pair using one or more direct current (DC) blocking elements that preserve an alternating current path. Power is injected onto the single conductor pair after the DC blocking elements and power is extracted from the single conductor pair before the DC blocking elements. Saturation of the data transformers by the injection of power onto the single pair is thereby prevented.

摘要翻译： 一种用于在单个导体对上实现电力应用的系统和方法。 在一个实施例中，使用保持交流路径的一个或多个直流（DC）阻塞元件将数据变压器耦合到单个导体对。 在直流阻塞元件之后，在直流阻塞元件之前从单个导体对提取功率，在单个导体对上注入功率。 从而防止了通过将电力注入到单对上的数据变压器的饱和度。

公开(公告)号：US20090058436A1

公开(公告)日：2009-03-05

申请号：US11849336

申请日：2007-09-03

申请人： James Yu

发明人： James Yu

IPC分类号： G01R27/02

CPC分类号： G01R27/04 ,  H04L12/10

摘要： A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

摘要翻译： 一种用于测量以太网供电（PoE）应用中的电缆电阻的系统和方法。 被动设备中的短路模块被设计成在接收到电缆电阻检测电压时产生短路效应。 电缆电阻检测电压可以被设计为大于用于检测或分类的电压，并且小于用于供电设备供电的电压。 电源设备产生短路效应时电流的测量可以计算给定PoE端口电缆的实际电阻。

公开(公告)号：US20050257010A1

公开(公告)日：2005-11-17

申请号：US11066038

申请日：2005-02-25

申请人： Phillip Jones ,  Paras Shah ,  James Yu ,  William Walker ,  Kenneth Jansen ,  Vasileios Balabanos ,  Andrew Olsen

发明人： Phillip Jones ,  Paras Shah ,  James Yu ,  William Walker ,  Kenneth Jansen ,  Vasileios Balabanos ,  Andrew Olsen

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

摘要翻译： 系统包括通过交换设备耦合在一起的多个节点。 每个节点包括耦合到存储器的处理器。 交换设备中的迁移逻辑被配置为将每个存储器的段迁移到交换设备。