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公开(公告)号：US20130136154A1
公开(公告)日：2013-05-30
申请号：US13481439
申请日：2012-05-25
IPC分类号： H04B1/713
CPC分类号： H04B1/709 , H04B1/7075 , H04B2201/70715
摘要： An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.
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22.发明授权Receivers, circuits, and methods to improve GNSS time-to-fix and other performances 有权接收器，电路和方法，以改善GNSS定时和其他性能公开(公告)号：US08441398B2
公开(公告)日：2013-05-14
申请号：US12726611
申请日：2010-03-18
摘要： An electronic circuit for a satellite receiver. The electronic circuit includes a correlator circuit operable to supply a data signal including ephemeris data and a subsequent satellite time datum, and a data processor operable to infer satellite time TS from as few as one of the ephemeris data prior to the satellite time datum. Other circuits, devices, receivers, systems, processes of operation and processes of manufacture are also disclosed.
摘要翻译： 一种用于卫星接收机的电子电路。 该电子电路包括可操作以提供包括星历数据和随后的卫星时间数据的数据信号的相关器电路，以及用于在卫星时间数据之前从少数几个星历数据推断卫星时间TS的数据处理器。 还公开了其它电路，设备，接收器，系统，操作过程和制造过程。
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23.发明申请DYNAMIC SWITCHING TO BIT-SYNCHRONOUS INTEGRATION TO IMPROVE GPS SIGNAL DETECTION 审中-公开动态切换到同步整合以改善GPS信号检测公开(公告)号：US20120319899A1
公开(公告)日：2012-12-20
申请号：US13161692
申请日：2011-06-16
IPC分类号： G01S19/30
CPC分类号： G01S19/246
摘要： A method includes determining a bit edge associated with information transmitted through a satellite during a detection operation of a receiver through a processor associated therewith. The method also includes dynamically switching, through the processor, a mode of a signal acquisition of the receiver from a current integration mode of operation of a measurement to a bit-synchronous integration mode of operation of the measurement using a processor when the bit edge is determined.
摘要翻译： 一种方法包括在通过与之相关的处理器在接收机的检测操作期间确定与通过卫星发送的信息相关联的位边沿。 该方法还包括通过处理器将接收机的信号采集模式从当前的测量操作模式转换为使用处理器的位同步整合操作模式，当位边沿为 决心。
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24.发明申请公开(公告)号：US20110248757A1
公开(公告)日：2011-10-13
申请号：US12756187
申请日：2010-04-08
申请人： SAKET JALAN , Raghu Ganesan , Jawaharlal Tangudu
发明人： SAKET JALAN , Raghu Ganesan , Jawaharlal Tangudu
IPC分类号： H03L7/00
CPC分类号： H03L7/0812
摘要： A digital calibration device and method for a high speed digital system. A digital calibration device coupled to a timing device in a high speed digital system for digitally calibrating the timing device includes a delay estimator, a control logic, and a digitally controlled load unit. In operation, the delay estimator calculates a delay value indicative of a timing delay between a first output and a second output of a timing device of the high speed digital system. Further, the control logic generates a control signal based on the delay value. Furthermore, the digitally controlled load unit applies at least one of a first load to a non-delayed line and a second load to a delayed line of the timing device based on the control signal to calibrate a timing delay between the non-delayed line and the delayed line of the timing device.
摘要翻译： 一种用于高速数字系统的数字校准装置和方法。 耦合到用于数字校准定时装置的高速数字系统中的定时装置的数字校准装置包括延迟估计器，控制逻辑和数字控制的负载单元。 在操作中，延迟估计器计算指示高速数字系统的定时装置的第一输出和第二输出之间的定时延迟的延迟值。 此外，控制逻辑基于延迟值产生控制信号。 此外，数字控制负载单元基于控制信号将至少一个负载施加到非延迟线和第二负载到定时装置的延迟线，以校准非延迟线和 定时装置的延迟线。
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25.发明申请RECEIVERS, CIRCUITS, AND METHODS TO IMPROVE GNSS TIME-TO-FIX AND OTHER PERFORMANCES 有权接收机，电路和方法，以改进全球定位系统时间到时间和其他性能公开(公告)号：US20110187596A1
公开(公告)日：2011-08-04
申请号：US12726611
申请日：2010-03-18
IPC分类号： G01S19/27
摘要： An electronic circuit (2250) for a satellite receiver (100, 2200). The electronic circuit (2250) includes a correlator circuit (2310) operable to supply a data signal including ephemeris data and a subsequent satellite time datum, and a data processor (2370, 2380) operable to infer satellite time TS from as few as one of the ephemeris data prior to the satellite time datum. Other circuits, devices, receivers, systems, processes of operation and processes of manufacture are also disclosed.
摘要翻译： 一种用于卫星接收机（100,2200）的电子电路（2250）。 电子电路（2250）包括可操作以提供包括星历数据和随后的卫星时间数据的数据信号的相关器电路（2310），以及数据处理器（2370,2808），其可操作以从至少一个 在卫星时间基准之前的星历数据。 还公开了其它电路，设备，接收器，系统，操作过程和制造过程。
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26.发明申请ENHANCED CROSS CORRELATION DETECTION OR MITIGATION CIRCUITS, PROCESSES, DEVICES, RECEIVERS AND SYSTEMS 有权增强交叉相关检测或缓解电路，过程，设备，接收器和系统公开(公告)号：US20110103432A1
公开(公告)日：2011-05-05
申请号：US12719965
申请日：2010-03-09
CPC分类号： G01S19/21 , H04B1/70755 , H04B2201/70715
摘要： A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes a correlator circuit (120) operable to correlate the signals with a selectable locally-issued PN code having a Doppler and a code lag to produce a peak, the correlator circuit (120) being subject to cross correlation with a distinct PN code carried by least one of the signals that can produce cross correlation; and a cross correlation circuit (370, 400) operable to generate a variable comparison value related to the cross correlation as a function of values representing a Doppler difference and a code lag difference between the locally-issued PN code and the distinct PN code, and to use the variable comparison value to reject the peak as invalid from cross correlation or to pass the peak as a valid received peak.
摘要翻译： 为不同信号强度的信号提供接收机（100），并用各自的伪随机噪声（PN）码进行调制。 接收器（100）包括相关器电路（120），其可操作以将信号与具有多普勒和码滞后的可选择本地发出的PN码相关以产生峰值，所述相关器电路（120）与 不同PN码携带的信号中至少有一个会产生互相关; 以及互相关电路（370,400），其可操作以根据表示本地发出的PN码和不同PN码之间的多普勒差和码滞差的值产生与互相关的可变比较值，以及 使用可变比较值将峰值从互相关中排除为无效，或将峰值作为有效接收峰值传递。
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27.发明授权公开(公告)号：US07817736B2
公开(公告)日：2010-10-19
申请号：US11770806
申请日：2007-06-29
IPC分类号： H04L27/28
CPC分类号： H04L27/2657 , H04L27/2671 , H04L27/2672 , H04L27/2675
摘要： A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency offset in a downconverted base-band multi-carrier signal in the frequency domain based on deviations of one or more characteristics of the pilot signals from predetermined values, and corrects for the offset in the time domain. In an embodiment, a second order phase locked loop (PLL) estimates the phase of the pilot signals to determine the carrier frequency offset. Changes in pilot phases caused due to the time domain correction are cancelled to allow the PLL to minimize deviations from the lock position.
摘要翻译： 多载波（MC）接收机接收包含数据符号以及导频符号的多载波信号。 MC接收机基于来自预定值的导频信号的一个或多个特性的偏差来估计频域中的下变频基带多载波信号中的载波频率偏移，并校正时域中的偏移。 在一个实施例中，二阶锁相环（PLL）估计导频信号的相位以确定载波频率偏移。 由于时域校正引起的导频相位的变化被取消，以允许PLL最小化与锁定位置的偏差。
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公开(公告)号：US20100119020A1
公开(公告)日：2010-05-13
申请号：US12505553
申请日：2009-07-20
摘要： An aspect of the present invention detects the presence of interference by examining an input signal received on an input path, and blanks the receiver if interference is detected. Information contained in the input signal may be recovered otherwise. In an embodiment, the duty cycle of a jamming signal is determined by examining the input signal, and a threshold strength having a positive correlation with the duty cycle is determined. If the strength of the jamming signal during the on-interval (start and end of the interference in each cycle) is greater than the threshold strength, then only the receiver is blanked. Otherwise, no blanking is performed, and only the gain of an amplifier in the path from the input path to a baseband processor is reduced. According to another aspect, one or more cycles of the interference is used to detect the start of interference and the receiver is blanked when interference is present.
摘要翻译： 本发明的一个方面通过检查在输入路径上接收到的输入信号来检测干扰的存在，如果检测到干扰，则对接收器进行空白。 包含在输入信号中的信息可以另外恢复。 在一个实施例中，通过检查输入信号来确定干扰信号的占空比，并确定与占空比正相关的阈值强度。 如果在间隔期间（每个周期的干扰的开始和结束）中的干扰信号的强度大于阈值强度，则仅接收机被消隐。 否则，不执行消隐，并且仅减少从输入路径到基带处理器的路径中的放大器的增益。 根据另一方面，使用干扰的一个或多个周期来检测干扰的开始，并且当存在干扰时接收机被消隐。
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29.发明申请公开(公告)号：US20090003493A1
公开(公告)日：2009-01-01
申请号：US11770806
申请日：2007-06-29
IPC分类号： H04L27/16
CPC分类号： H04L27/2657 , H04L27/2671 , H04L27/2672 , H04L27/2675
摘要： A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency offset in a downconverted base-band multi-carrier signal in the frequency domain based on deviations of one or more characteristics of the pilot signals from predetermined values, and corrects for the offset in the time domain. In an embodiment, a second order phase locked loop (PLL) estimates the phase of the pilot signals to determine the carrier frequency offset. Changes in pilot phases caused due to the time domain correction are cancelled to allow the PLL to minimize deviations from the lock position.
摘要翻译： 多载波（MC）接收机接收包含数据符号以及导频符号的多载波信号。 MC接收机基于来自预定值的导频信号的一个或多个特性的偏差来估计频域中的下变频基带多载波信号中的载波频率偏移，并校正时域中的偏移。 在一个实施例中，二阶锁相环（PLL）估计导频信号的相位以确定载波频率偏移。 由于时域校正引起的导频相位的变化被取消，以允许PLL最小化与锁定位置的偏差。
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